We consider radio applications in sensor networks, where the nodes operate on batteries so that energy consumption must be minimized, while satisfying given throughput and delay requirements. In this context, we analyze the best modulation and transmission strategy to minimize the total energy consumption required to send a given number of bits. The total energy consumption includes both the transmission energy and the circuit energy consumption. We first consider multi-input-multi-output (MIMO) systems based on Alamouti diversity schemes, which have good spectral efficiency but also more circuitry that consumes energy. We then extend our energy-efficiency analysis of MIMO systems to individual single-antenna nodes that cooperate to form multiple-antenna transmitters or receivers. By transmitting and/or receiving information jointly, we show that tremendous energy saving is possible for transmission distances larger than a given threshold, even when we take into account the local energy cost necessary for joint information transmission and reception. We also show that over some distance ranges, cooperative MIMO transmission and reception can simultaneously achieve both energy savings and delay reduction.

Energy-efficiency of MIMO and cooperative MIMO techniques in sensor networks

Wireless systems where the nodes operate on batteries so that energy consumption must be minimized while satisfying given throughput and delay requirements are considered. In this context, the best modulation strategy to minimize the total energy consumption required to send a given number of bits is analyzed. The total energy consumption includes both the transmission energy and the circuit energy consumption. For uncoded systems, by optimizing the transmission time and the modulation parameters, it is shown that up to 80% energy savings is achievable over nonoptimized systems. For coded systems, it is shown that the benefit of coding varies with the transmission distance and the underlying modulation schemes.

Energy-constrained modulation optimization

Based on a physical understanding of phase-noise mechanisms, a passive LC filter is found to lower the phase-noise factor in a differential oscillator to its fundamental minimum. Three fully integrated LC voltage-controlled oscillators (VCOs) serve as a proof of concept. Two 1.1-GHz VCOs achieve -153 dBc/Hz at 3 MHz offset, biased at 3.7 mA from 2.5 V. A 2.1-GHz VCO achieves -148 dBc/Hz at 15 MHz offset, taking 4 mA from a 2.7-V supply. All oscillators use fully integrated resonators, and the first two exceed discrete transistor modules in figure of merit. Practical aspects and repercussions of the technique are discussed.

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A filtering technique to lower LC oscillator phase noise

This paper describes the design and optimization of VCOs with quadrature outputs. Systematic design of fully integrated LC-VCOs with a high inductance tank leads to a cross-coupled double core LC-VCO as the optimal solution in terms of power consumption. Furthermore, a novel fully differential frequency tuning concept is introduced to ease high integration. The concepts are verified with a 0.25-/spl mu/m standard CMOS fully integrated quadrature VCO for zero- or low-IF DCS1800, DECT, or GSM receivers. At 2.5-V power supply voltage and a total power dissipation of 20 mW, the quadrature VCO features a worst-case phase noise of -143 dBc/Hz at 3-MHz frequency offset over the tuning range. The oscillator is tuned from 1.71 to 1.99 GHz through a differential nMOS/pMOS varactor input.

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Low-power low-phase-noise differentially tuned quadrature VCO design in standard CMOS

This paper presents a quadrature voltage-controlled oscillator (QVCO) based on the coupling of two LC-tank VCOs A simplified theoretical analysis for the oscillation frequency and phase noise displayed by the QVCO in the 1/f/sup 3/ region is developed, and good agreement is found between theory and simulation results A prototype for the QVCO was implemented in a 035-/spl mu/m CMOS process with three standard metal layers The QVCO could be tuned between 164 and 197 GHz, and showed a phase noise of -140 dBc/Hz or less across the tuning range at a 3-MHz offset frequency from the carrier, for a current consumption of 25 mA from a 2-V power supply The equivalent phase error between I and Q signals was at most 025/spl deg/

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Analysis and design of a 1.8-GHz CMOS LC quadrature VCO

This work presents the design and implementation of a 2-V cellular transceiver front-end in a standard 0.25-/spl mu/m CMOS technology. The prototype integrates a low-IF receiver (low noise amplifier, I/Q mixers, and VGAs) and a direct-upconversion transmitter (I/Q mixers and pre-amplifier) on a single die together with a complete phase-locked loop, including a 64/79 prescaler, a fully integrated loop filter, and a quadrature voltage controlled oscillator with on-chip inductors. Design trade-offs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low voltage. As a result, the IC operates from a power supply of only 2 V, while consuming 191 mW in receiver (RX) mode and 160 mW in transmitter (TX) mode. To build a complete transceiver system for 1,8-GHz cellular communication, only an antenna, an antenna filter, a power amplifier, and a digital baseband chip must be added to the analog front-end. This work shows the potential of achieving the analog performance required for the class I/II DCS-1800 cellular system in a standard 0.25-/spl mu/m CMOS technology, without tuning or trimming.

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A 2 V CMOS cellular transceiver front-end

A fully integrated 2-GHz very low-phase-noise LC-tank voltage-controlled oscillator (VCO) set with flicker noise upconversion minimization is presented. Using only integrated planar inductors, the measured phase noise is as low as -125.1 dBc/Hz at 600-kHz offset and -138 dBc/Hz at 3 MHz. The excellent phase-noise performance is achieved by means of an in-house-developed integrated inductor simulator optimizer. To minimize the upconversion of flicker noise to 1/f/sup 3/ phase noise, a flicker-noise upconversion factor is defined, which can easily be extracted from circuit simulation. The technique is applied to demonstrate the relationship between the flicker-noise upconversion and the overdrive level of the oscillators' MOS cross-coupled pair and to develop circuit balancing techniques to even further reduce the flicker-noise upconversion. The 1/f/sup 3/ phase-noise corner is minimized to be less than 15 kHz. The VCO's are implemented in a three-metal layer, 0.65-/spl mu/m BiCMOS process, using only MOS active devices.

A 2-GHz low-phase-noise integrated LC-VCO set with flicker-noise upconversion minimization

Research over the last ten years has resulted in attempts toward single-chip CMOS RF circuits for Bluetooth, global positioning system, digital enhanced cordless telecommunications and cellular applications. An overview of the use of CMOS for low-cost integration of a high-end cellular RF transceiver front-end is presented. Some fundamental pitfalls and limitations of RF CMOS are discussed. To circumvent these obstacles, the choice of transceiver architecture, circuit topology design, and systematic optimization of the different transceiver blocks is necessary. Moreover, optimization of the transceiver as one single block by minimizing the number of power-hungry interface circuits is emphasized. As examples, a fully integrated cellular transceiver front-end, a low-power extremely low noise-figure low-noise amplifier, and a very efficient power amplifier are demonstrated.

Low-voltage low-power CMOS-RF transceiver design

This CMOS transceiver chip for the DCS-1800 wireless communication system is realized in a 0.25 /spl mu/m CMOS process. The realization of a CMOS transceiver that complies with the specifications of a high-quality digital-wireless system requires overall integration of architecture, building block and transistor-level design. A highly-integrated architecture minimizes the number of high-frequency external nodes, as these are difficult to drive with CMOS circuits. Up- and downconversion topologies allow at the same time mixing and a high-quality on-chip single-ended to differential conversion. Extra buffers between building blocks optimize overall circuit performance.

A single-chip CMOS transceiver for DCS-1800 wireless communications

A 1.8 GHz fully integrated Voltage Controlled Oscillator (VCO) is presented. Through inductor optimization, the phase noise is as low as -127.5 dBc/Hz at 600 kHz and -142.5 dBc/Hz at 3 MHz. A 28% wide tuning range is achieved with a 1.8 V power supply. The VCO exceeds the DCS-1800 phase noise requirements with at least 4 dB over the whole DCS-1800 frequency band. The VCO is implemented in a 2-metal layer, 0.25 /spl mu/m standard CMOS technology, using no external components nor additional processing steps.

M. Borremans

Papers

A 2 V CMOS cellular transceiver front-end

A 2-GHz low-phase-noise integrated LC-VCO set with flicker-noise upconversion minimization

Low-voltage low-power CMOS-RF transceiver design

A single-chip CMOS transceiver for DCS-1800 wireless communications

A 1.8 GHz highly-tunable low-phase-noise CMOS VCO