High temperature effects on CMOS transconductance (g/sub m/) are investigated in linear and saturation regions. Measured g/sub m/ in the saturation region at temperatures between 27-200/spl deg/C were observed to intersect at one gate bias point. However, no such point was observed in the linear region. Similar characteristics was produced using analytical MOSFET current model that incorporate temperature dependence of device parameters.

Investigation of high temperature effects on MOSFET transconductance (g/sub m/)

This paper presents a detailed study of the RF and noise performance of n-type Schottky barrier (SB) MOSFETs with a particular focus on the influence of the Schottky barrier height (SBH) on the main dynamic and noise figures of merit. With this aim, a 2D Monte Carlo simulator including tunnelling transport across Schottky interfaces has been developed, with special care to consider quantum transmission coefficients and the influence of image charge effects at the Schottky junctions. Particular attention is paid to the microscopic transport features, including carrier mean free paths or number of scattering events along the channel for investigating the optimization of the device topology and the strategic concepts related to the noise performance of this new architecture. A more effective control of the gate electrode over drain current for low SBH (discussed in terms of internal physical quantities) is translated into an enhanced transconductance gm, cut-off frequency fT, and non-quasistatic dynamic parameters. The drain and gate intrinsic noise sources show a noteworthy degradation with the SBH reduction due to the increased current, influence of hot carriers and reduced number of phonon scatterings. However, the results evidence that this effect is counterbalanced by the extremely improved dynamic performance in terms of gm and fT. Therefore, the deterioration of the intrinsic noise performance of the SB-MOSFET has no significant impact on high-frequency noise FoMs as NFmin, Rn and Gass for low SBH and large gate overdrive conditions. The role of the SBH on Γopt, optimum noise reactance and susceptance has been also analyzed.

RF dynamic and noise performance of Metallic Source/Drain SOI n-MOSFETs

The analog/radio frequency (RF) and linearity performance of a junctionless double gate metal–oxide–semiconductor field-effect transistor (JL DGMOS) is investigated using the numerical TCAD device simulator. JL DGMOSs have shown great promise for high-performance digital applications due to their superior short channel effect performance and ease of fabrication. In analog and RF circuit applications, linearity testing and RF performance is a major issue that is encountered due to non-linear behavior of the devices. Therefore, in this paper, different RF/analog and linearity performance figures of merits such as transconductance, intrinsic gain, the transconductance generation factor, the cut off frequency, the maximum frequency of oscillation, the gain bandwidth product, the variable intercept point of second order, the variable intercept point of third order, inter modulation distortion, the third-order intercept point, and 1-dB compression have been presented. Moreover, the effect of gate-length downsca...

Radio frequency/analog and linearity performance of a junctionless double gate metal–oxide–semiconductor field-effect transistor:

Our experiments show that linearity can be achieved if transistors are designed to operate in the one-dimensional ballistic transport regime in the quantum capacitance limit. We report third order intercept points (IIP3) of around −13dBm at maximum transconductance under these particular transport and device operation conditions, meeting the requirements for state-of-the-art mobile communication systems. The advantage of our approach becomes most apparent when normalizing the IIP3 values with power at maximum transconductance. In this case we were able to show that more than 10dB improvement over devices operating in the velocity saturation regime is achieved. Our findings make our approach an excellent candidate for low power applications in the early stages of RF receivers when linearity is critical.

A new method to achieve RF linearity in SOI nanowire MOSFETs

The Analog/Radio Frequency and Linearity analysis of a III-V Heterostructure Underlap Double Gate MOSFET is done using the numerical TCAD device simulator. Heterostructure Underlap DGMOS has evolved as a strong contender for various digital application. In analog and RF circuit application, linearity testing and RF performance confronts as a major problem which develops due to non linearity of the devices. In this paper, different figure of merits like Transconductance(gm), Transconductance Generation Factor (gm/ID), Cut off frequency(fT), Variable Intercept Point of Second order(VIP2)are analyzed. The comparative study with Junctionless Double Gate MOSFET has been carried out. The results reveal that Heterostucture DGMOS shows great promise to become a competitive contender for Analog/Mixed signal System-On-Chip (SOC) application by demonstrating a significant improvement in its RF performance.

Performance investigation of III-V heterosturucture underlap double gate MOSFET for System-On-Chip application

By considering several secondary effects including the channel length modulation, mobility degradation, drain induced barrier lowering, and threshold voltage variation, an accurate saturation transconductance model for short-channel MOSFETs is developed. The calculated values of saturation transconductance agree well with the BSIM3 simulation results and the experimental results for devices with effective channel length in the range of 0.44-10 μm. This model has the advantages of less number of model parameters and can be used to analyze the small signal performance of analog circuits.

M.C. Poon

Papers

Modeling of saturation transconductance for short-channel MOSFETs