The techniques known in literature for the design of SRAM structures with low standby leakage typically exploit an additional operation mode, named the sleep mode or the standby mode. In this paper, existing low leakage SRAM structures are analyzed by several SPEC2000 benchmarks. As expected, the examined SRAM architectures have static power consumption lower than the conventional 6-T SRAM cell. However, the additional activities performed to enter and to exit the sleep mode also lead to higher dynamic energy. Our study demonstrates that, due to this, the overall energy consumption achieved by the known low-leakage techniques is greater than the conventional approach. In the second part of this paper, a novel low-leakage SRAM cell is presented. The proposed structure establishes when to enter and to exit the sleep mode, on the basis of the data stored in it, without introducing time and energy penalties with respect to the conventional 6-T cell. The new SRAM structure was realized using the UMC 0.18-mum, 1.8-V, and the ST 90-nm 1-V CMOS technologies. Tests performed with a set of SPEC2000 benchmarks have shown that the proposed approach is actually energy efficient

Techniques for Leakage Energy Reduction in Deep Submicrometer Cache Memories

Tremendous progress in information technology has been made possible by the development and optimization of metal oxide semiconductor field effect transistor (MOSFET) devices. For the last three decades, the dimensions of the devices have been scaled down and the complexity of the integrated circuits increased according to Moore’s law. Further scaling of the devices has been predicted by the international technology roadmap for semiconductors (ITRS). To meet the future technological requirements, much effort has been expended on increasing the capabilities of MOSFETs. Both new materials and new designs have been introduced to maintain device scaling. Most new designs were improvements of the normal planar design of the device, such as SOI and ultrathin body devices. In so-called FinFET structures, current flows through a thin silicon fin and is controlled by two gates in parallel on both sides of the fin. Vertical MOSFET devices represent a new category. In these structures the planar arrangement of the source gate and drain is turned through 90° so that they are positioned on top of each other and the current flow is perpendicular to the surface. By utilizing the 3rd dimension, the channel length can be adjusted by layer deposition and thus dispensing with advanced (and expensive) lithography. Furthermore, depending on the application, the vertical designs require less space than planar ones so that it is possible to increase integration density. The present paper gives a review of vertical MOSFET devices with current flow perpendicular to the surface.

Turning the world vertical: MOSFETs with current flow perpendicular to the wafer surface

This paper is based on the observation of a CMOS five-transistor SRAM cell (5T SRAM cell) for very high density and low power applications. This cell retains its data with leakage current and positive feedback without refresh cycle. This 5T SRAM cell uses one word-line and one bit-line and extra read-line control. The new cell size is 21.66% smaller than a conventional six-transistor SRAM cell using same design rules with no performance degradation. Simulation and analytical results show purposed cell has correct operation during read/write and also the delay of new cell is 70.15% smaller than a six-transistor SRAM cell. The new 5T SRAM cell contains 72.10% less leakage current with respect to the 6T SRAM memory cell using cadence 45 nm technology.

https://www.imt.ro/romjist/Volum15/Number15_2/06-SAkashe.pdf

High density and low leakage current based 5T SRAM cell using 45 nm technology

Based on the observation that dynamic occurrences of zeros in the cache access stream and cache-resident memory values of ordinary programs exhibit a strong bias towards zero, this paper presents a novel CMOS four-transistor SRAM cell (4T SRAM cell) for very high density and low power cache applications. This cell retains its data with leakage current and positive feedback without refresh cycle. Novel 4T SRAM cell uses two word-lines and one pair bit-line. The new cell size is 20% smaller than a conventional six-transistor cell (6T SRAM cell) using same design rules and average delay access of a cache based on new 4T SRAM cell is 30% smaller than a cache based on 6T SRAM cell. Also the average dynamic energy consumption during cache access of new cell is 45% smaller than 6T SRAM cell.

A Novel Zero-Aware Four-Transistor SRAM Cell for High Density and Low Power Cache Application

This paper presents a novel CMOS four-transistor SRAM cell for very high density and low power embedded SRAM applications as well as for stand-alone SRAM applications. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 20% smaller than a conventional six-transistor cell using same design rules. Also proposed cell uses two word-lines and one pair bit-line. Read operation perform from one side of cell, and write operation perform from another side of cell, and swing voltage reduced on word-lines thus dynamic power during read/write operation reduced. The fabrication process is fully compatible with high-performance CMOS logic technologies, because there is no need to integrate a poly-Si resistor or a TFT load. HSPICE simulation in standard 0.25μm CMOS technology confirms all results obtained from this paper. Keywords—Positive feedback, leakage current, read operation, write operation, dynamic energy consumption.

A Novel Four-Transistor SRAM Cell with Low Dynamic Power Consumption

To realize high-density SRAMs, we developed a four-transistor SRAM cell with a newly developed stacked vertical poly-silicon PMOS The vertical poly-silicon PMOS has a gate surrounding a body that forms a channel and yields a drive current of 20 /spl mu/A at 25/spl deg/C Vertical poly-silicon PMOSs are used as transfer MOSs and are stacked over the bulk NMOSs, used as driver MOSs, to reduce the size of a four-transistor SRAM cell As a result, the size of the proposed four-transistor SRAM cell was 38% of that of a six-transistor SRAM cell We also developed an electric-field-relaxation scheme to reduce cell leakage and a dual-word-voltage scheme to improve cell stability By applying these two schemes to the proposed four-transistor SRAM cell, we achieved a 90% reduction in cell leakage and an improvement in cell stability

A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme

We developed a four-transistor SRAM cell with a vertically stacked poly-silicon MOS. Its size-fabricated by using 0.13-/spl mu/m technology - is 0.78 /spl mu/m/sup 2/, that is, only 38% of that of a six-transistor SRAM cell. By optimizing the threshold voltages and the gate-oxide thicknesses of the cell transistors, and developing a modified electric-field-relaxation scheme, an estimated cell leakage current of 88.7 fA/cell was achieved. We also developed a dual-word-voltage scheme to achieve stable operation of the cell during a read operation without affecting a write operation.

M. Fujioka

Papers

A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme

A 0.13-/spl mu/m, 0.78-/spl mu/m/sup 2/ low-power four-transistor SRAM cell with a vertically stacked poly-silicon MOS and a dual-word-voltage scheme