This paper describes low-voltage random-access memory (RAM) cells and peripheral circuits for standalone and embedded RAMs, focusing on stable operation and reduced subthreshold current in standby and active modes. First, technology trends in low-voltage dynamic RAMs (DRAMs) and static RAMs (SRAMs) are reviewed and the challenges of low-voltage RAMs in terms of cell signal charge are clarified, including the necessary threshold voltage, VT, and its variations in the MOS field-effect transistors (MOSFETs) of RAM cells and sense amplifiers, leakage currents (subthreshold current and gate-tunnel current), and speed variations resulting from design parameter variations. Second, developments in conventional RAM cells and emerging cells, such as DRAM gain cells and leakage-immune SRAM cells, are discussed from the viewpoints of cell area, operating voltage, and leakage currents of MOSFETs. Third, the concepts proposed to date to reduce subthreshold current and the advantages of RAMs with respect to reducing the subthreshold current are summarized, including their applications to RAM circuits to reduce the current in standby and active modes, exemplified by DRAMs. After this, design issues in other peripheral circuits, such as sense amplifiers and low-voltage supporting circuits, are discussed, as are power management to suppress speed variations and reduce the power of power-aware systems, and testing. Finally, future prospects based on the above discussion are examined.

Review and future prospects of low-voltage RAM circuits

In recent years, reducing power has become an important design goal for high-performance microprocessors. This work attempts to bring the power issue to the earliest phases of microprocessor development, in particular, the stage of defining a chip microarchitecture. We investigate power-optimization techniques of superscalar microprocessors at the microarchitecture level that do not compromise performance. First, major targets for power reduction are identified within microarchitecture, where power is heavily consumed or will be heavily consumed in next-generation superscalar processors. Then, a new, energy-efficient version of a multicluster microarchitecture is developed that reduces energy the identified critical design points with minimal performance impact. A methodology is developed for energy-performance optimization at the microarchitecture level that generates, for a microarchitecture, a set of energy-efficient configurations, forming a convex hull in the power-performance space. Detailed simulation of the baseline and proposed multicluster architectures has been performed using the developed optimization methodology. A comparison of the two microarchitectures, both optimized for energy efficiency, shows that the multicluster architecture is potentially up to twice as energy efficient for wide issue processors, with an advantage that Grows with the issue width. Conversely, at the same power dissipation level, the multicluster architecture supports configurations with measurably higher performance than equivalent conventional designs.

Inherently lower-power high-performance superscalar architectures

Register files (RF) represent a substantial portion of the energy budget in modern processors, and are growing rapidly with the trend towards wider instruction issue. The actual access energy costs depend greatly on the register file circuitry used. This paper compares various RF circuitry techniques for their energy ef- ficiencies, as a function of architectural parameters such as the number of registers and the number of ports. The Port Priority Selection technique was found to be the most energy efficient. The dependence of register file access energy upon technology scaling is also studied. However, as this paper shows, it appears that none of these will be enough to prevent centralized register files from becoming the dominant power component of next-generation superscalar computers, and alternative methods for inter-instruction communication need to be developed. Split register file architecture is analyzed as a possible alternative.

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The energy complexity of register files

The digital low dropout regulator (D-LDO) has drawn significant attention recently for its low-voltage operation and process scalability. However, the tradeoff between current efficiency and transient response speed has limited its applications. In this brief, a coarse–fine-tuning technique with burst-mode operation is proposed to the D-LDO. Once the voltage undershoot/overshoot is detected, the coarse tuning quickly finds out the coarse control word in which the load current should be located, with large power MOS strength and high sampling frequency for a fixed time. Then, the fine-tuning, with reduced power MOS strength and sampling frequency, regulates the D-LDO to the desired output voltage and takes over the steady-state operation for high accuracy and current efficiency. The proposed D-LDO is verified in a 65-nm CMOS process with a 0.01-mm2 active area. The measured voltage undershoot and overshoot are 55 and 47 mV, respectively, with load steps of 2 to 100 mA with a 20-ns edge time. The quiescent current is 82 $\mu\textrm{A}$ , with a 0.43-ps figure of merit achieved. Moreover, the reference tracking speed is 1.5 $\textrm{V}/\mu\textrm{s}$ .

A Fully Integrated Digital LDO With Coarse–Fine-Tuning and Burst-Mode Operation

A digital DLL apparatus and a method for correcting a duty cycle are disclosed. The apparatus includes: a delay line unit for receiving external clock signal and generating first and second delayed internal clock signals by delaying the external clock signal; a duty error controller for receiving the first and second delayed clock signals and outputting a first duty controlled clock signal and second duty controlled clock signal by shifting edges of the first and second delayed internal clock signals; and a delay model unit for compensating a delay of the duty controlled clock signal by estimating a delay amount of system. The present invention can correct the duty error by using the phase mixer and generate an internal clock signal having 50% of duty cycle.

Digital DLL apparatus for correcting duty cycle and method thereof

A fast transient-response digital low-dropout (LDO) voltage regulator comprising only low-voltage MOS transistors was developed. The input voltage can be higher than the withstand voltage of the low-voltage MOS transistors by the proposed withstand-voltage relaxation scheme. The switching frequency of 1 GHz can be achieved using small-dimension low-voltage power-MOS transistors. The LDO occupies only 0.057 mm2 area using 40-nm CMOS technology, and covers a wide range of load currents from 400 μA to 250 mA. The response time is only 0.07 μs.

A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process

A 16-Mb CMOS SRAM using 0.4-/spl mu/m CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm/sup 2/ is fabricated and an address access time of 12.5 ns has been achieved. >

A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers

To realize high-density SRAMs, we developed a four-transistor SRAM cell with a newly developed stacked vertical poly-silicon PMOS The vertical poly-silicon PMOS has a gate surrounding a body that forms a channel and yields a drive current of 20 /spl mu/A at 25/spl deg/C Vertical poly-silicon PMOSs are used as transfer MOSs and are stacked over the bulk NMOSs, used as driver MOSs, to reduce the size of a four-transistor SRAM cell As a result, the size of the proposed four-transistor SRAM cell was 38% of that of a six-transistor SRAM cell We also developed an electric-field-relaxation scheme to reduce cell leakage and a dual-word-voltage scheme to improve cell stability By applying these two schemes to the proposed four-transistor SRAM cell, we achieved a 90% reduction in cell leakage and an improvement in cell stability

A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme

PURPOSE: To allow the system to immediately trace the internal clock signal of a peripheral circuit when the clock signal frequency of the system is switched. CONSTITUTION: A 1st clock signal PCLK and a 2nd clock signal CLK with a frequency equal to that of the 1st clock signal and whose phase is delayed by a prescribed time are generated by a clock pulse generator 10 and peripheral circuits 2, 3 receive both the clock signals and are operated synchronously with each other. Delay locked loop circuits 20, 30 use a variable delay means to delay the 1st clock signal PCLK thereby generating an internal clock signal ICLK and a phase difference detection means detects a phase difference between the internal clock signal ICLK and the 2nd clock signal CLK and a delay time by the variable delay means is controlled to cancel the detected phase difference.

Data processing system and semiconductor integrated circuit

PROBLEM TO BE SOLVED: To reduce power consumption of a semiconductor device which has a differential input buffer between itself and an external interface circuit. SOLUTION: The semiconductor device has a differential input buffer 1 and a latch circuit 2 having its input connected to the output of the differential input buffer. The differential input buffer 1 has a differential input amplifier which inputs a reference potential Vref and an external signal IN differentially, a power switch Q5 which supplies a high-potential side current to the differential amplifier, and a 2nd power switch Q6 which supplies a low-potential side current to the differential input amplifier. A control circuit 3 controls the differential input buffer 1 into alternate active and inactive states according to the state of a synchronizing clock signal QCLKb and also controls the latch circuit 2 into input and latch states synchronously, so a through current is prevented from always passing through the differential input buffer 1, thereby reducing the power consumption of the semiconductor device. COPYRIGHT: (C)1999,JPO

Sadayuki Morita

Papers

A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process

A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers

A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme

Data processing system and semiconductor integrated circuit

Semiconductor device and data processing system