FastCap : A Multipole Accelerated 3-D Capacitance Extraction Program

Bundles of single-walled carbon nanotubes (SWCNTs) have been proposed as a possible replacement for on-chip copper interconnect due to their large conductivity and current-carrying capabilities. Given the manufacturing challenges associated with future nanotube-based interconnect solutions, determining the impact of process variations on this new technology relative to standard copper interconnect is vital for predicting the reliability of nanotube-based interconnect. In this paper, we investigate the impact of process variations on future interconnect solutions based on carbon nanotube bundles. Leveraging an equivalent RLC model for SWCNT bundle interconnect, we calculate the relative impact of ten potential sources of variation in SWCNT bundle interconnect on resistance, capacitance, inductance, and delay. We compare the relative impact of variation for SWCNT bundles and standard copper wires as process technology scales and find that SWCNT bundle interconnect will typically have larger overall three-sigma variations in delay. In order to achieve the same percentage variation in both SWCNT bundles and copper interconnect, the percentage variation in bundle dimensions must be reduced by up to 63% in 22-nm process technology

On the Impact of Process Variations for Carbon Nanotube Bundles for VLSI Interconnect

Given the spatial and temporal randomness of soft and permanent errors in the state-of-the-art system-on-chips (SoCs), dynamic routing algorithms that can adapt themselves accordingly are highly required for network-on-chip (NoC) applications. In this paper, we present a new dynamic routing algorithm for NoC applications that has the ability to locate and deal with both static and dynamic permanent failures and distinguish them from soft errors. In addition, our presented algorithm has the advantage of distributing the load over the whole network by considering the stress factors. Simulation results demonstrate the advantage of our routing algorithm in terms of functionality, latency, and energy consumption compared to directed flooding based fault tolerant routing algorithms in the presence of both soft errors and permanent faults. Our algorithm can achieves 1.95 times less latency and consumes 3.15 times less energy consumption on average.

A fault-aware dynamic routing algorithm for on-chip networks

3D integration of multiple active layers into a single chip is a viable technique that greatly reduces the length of global wires by providing vertical connections between layers. However, dissipating the heat generated in the 3D chips possesses a major challenge to the success of the technology and is the subject of active current research. Since the generated heat degrades the performance of the chip, thermally insensitive/adaptive circuit design techniques are required for better overall system performance. In this paper, we propose a thermally adaptive 3D clocking scheme that dynamically adjusts the driving strengths of the clock buffers to reduce the clock skew between terminals. We investigate the relative merits and demerits of two alternative clock tree topologies in this work. Simulation results demonstrate that our adaptive technique is capable of reducing the skew by 61.65% on the average, leading to much improved clock synchronization and design performance in the 3D realm.

/pdf/thermally-robust-clocking-schemes-for-3d-integrated-circuits-543sde6p3y.pdf

Thermally robust clocking schemes for 3D integrated circuits

This book discusses new techniques for detecting, controlling, and exploiting the impacts of temperature variations on nanoscale circuits and systems. A new sensor system is described that can determine the temperature dependence as well as the operating temperature to improve system reliability. A new method is presented to control a circuit’s temperature dependence by individually tuning pull-up and pull-down networks to their temperature-insensitive operating points. This method extends the range of supply voltages that can be made temperatureinsensitive, achieving insensitivity at nominal voltage for the first time.

/pdf/managing-temperature-effects-in-nanoscale-adaptive-systems-2dxgqzvtby.pdf

Managing Temperature Effects in Nanoscale Adaptive Systems

A network-on-chip (NoC) replaces on-chip communication implemented by point-to-point interconnects in a multi-core environment by a set of shared interconnects connected through programmable crosspoints. Since an NoC may provide a number of paths between a given source and destination, manufacturing or runtime faults on one interconnect does not necessarily render the chip useless. It is partly because of this fault tolerance that NoCs have emerged as a viable alternative for implementing communication between functional units of a chip in the nanometer regime, where high defect rates are prevalent. In this paper, the authors quantify the fault tolerance offered by an NoC against process variations. Specifically, the authors develop an analytical model for the probability of failure in buffered global NoC links due to interconnect dishing, and effective channel length variation. Using the developed probability model, the authors study the impact of link failure on the number of cycles required to establish communications in NoC applications

Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations

On-chip temperature gradient emerged as a major design concern for high performance integrated circuits for the current and future technology nodes. Clock skew is an undesirable phenomenon for synchronous digital circuits that is exacerbated by the temperature difference between various parts of the clock tree. We investigate the effect of on-chip temperature gradient on the clock skew for a number of temperature profiles. As an effective way of mitigating the clock skew, we present an adaptive circuit technique that senses the temperature of different parts of the clock tree and adjusts the driving strengths of the corresponding clock buffers dynamically to reduce the clock skew. Simulation results demonstrate that with minimal area overhead our adaptive technique is capable of reducing the skew by 72.4%, on the average, leading to much improved clock synchronization and design performance

Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers

This paper studies the impact of variability on the noise robustness of logic gates using noise rejection curves (NRCs). NRCs allow noise pulses to be modeled using magnitude-duration profiles, and can be used to derive a noise susceptibility metric for the noise robustness of logic gates. Analytical methods - based upon calibration runs in circuit simulators - to determine noise susceptibility in the presence of variations in process, design, and environmental parameters (Leff, VT, VDD, and W) are described. Such analytical methods can be used not only to accurately estimate the impact of variability on noise robustness, but also to optimize designs for noise robustness

https://www.pitt.edu/~kmram/publications/isqed07.pdf

Parameter-Variation-Aware Analysis for Noise Robustness

On-chip temperature gradient has emerged as a major design concern for high-performance integrated circuits for the current and future technology nodes. Clock skew is an undesirable phenomenon for synchronous digital circuits that is exacerbated by the temperature difference between various parts of the clock tree. The main aim of this paper is to provide intelligent solution for minimizing the temperature-dependent clock skew by designing dynamically adaptive circuit elements, particularly the clock buffers. Using an RLC model of the clock tree, we investigate the effect of on-chip temperature gradient on the clock skew for a number of temperature profiles that can arise in practice due to different architectures and applications. As an effective way of mitigating the variable clock skew, we present an adaptive circuit technique that senses the temperature of different parts of the clock tree and adjusts the driving strengths of the corresponding clock buffers dynamically to reduce the clock skew. Simulation results demonstrate that our adaptive technique is capable of reducing the skew by up to 92.4%, leading to much improved clock synchronization and design performance.

M. Mondal

Papers

Thermally robust clocking schemes for 3D integrated circuits

Provisioning On-Chip Networks under Buffered RC Interconnect Delay Variations

Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers

Parameter-Variation-Aware Analysis for Noise Robustness

Design of Thermally Robust Clock Trees Using Dynamically Adaptive Clock Buffers