Proceedings ArticleDOI
Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers
M. Mondal,A. Ricketts,S. Kirolos,T. Ragheb,G. M. Link,Vijaykrishnan Narayanan,Yehia Massoud +6 more
- pp 67-72
TLDR
An adaptive circuit technique is presented that senses the temperature of different parts of the clock tree and adjusts the driving strengths of the corresponding clock buffers dynamically to reduce the clock skew, leading to much improved clock synchronization and design performance.Abstract:
On-chip temperature gradient emerged as a major design concern for high performance integrated circuits for the current and future technology nodes. Clock skew is an undesirable phenomenon for synchronous digital circuits that is exacerbated by the temperature difference between various parts of the clock tree. We investigate the effect of on-chip temperature gradient on the clock skew for a number of temperature profiles. As an effective way of mitigating the clock skew, we present an adaptive circuit technique that senses the temperature of different parts of the clock tree and adjusts the driving strengths of the corresponding clock buffers dynamically to reduce the clock skew. Simulation results demonstrate that with minimal area overhead our adaptive technique is capable of reducing the skew by 72.4%, on the average, leading to much improved clock synchronization and design performanceread more
Citations
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Proceedings ArticleDOI
Thermally robust clocking schemes for 3D integrated circuits
TL;DR: This work proposes a thermally adaptive 3D clocking scheme that dynamically adjusts the driving strengths of the clock buffers to reduce the clock skew between terminals, leading to much improved clock synchronization and design performance in the 3D realm.
Proceedings ArticleDOI
Adaptive clock distribution for 3D integrated circuits
TL;DR: A robust tunable-delay-buffer circuit and a novel active de-skew method are developed in order to handle the cross-die variations, thermal gradients, and wiring asymmetry in 3D ICs.
Journal ArticleDOI
Adaptive and Reliable Clock Distribution Design for 3-D Integrated Circuits
TL;DR: A novel active deskew technique to adaptively mitigate the cross-tier variations and the 3-D wiring asymmetry is proposed and a thermal profile-based optimization flow is developed to further improve the power efficiency and reduce design overhead.
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