A semiconductor component having a semiconductor body comprises a blocking pn junction, a source zone of a first conductivity type and bordering on a zone forming the blocking pn junction of a second conductivity type complementary to the first conductivity type, and a drain zone of the first conductivity type. The side of the zone of the second conductivity type faces the drain zone forming a first surface, and in the region between the first surface and a second surface areas of the first and second conductivity type are nested in one another. The areas of the first and second conductivity type are variably so doped that near the first surface doping atoms of the second conductivity type predominate, and near the second surface doping atoms of the first conductivity type predominate. Furthermore a plurality of floating zones of the first and second conductivity type is provided.

High-voltage semiconductor component

A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region. A filler material is deposited in the terraced trench to substantially fill the trench, thus completing the voltage sustaining region. At least one region of the I second conductivity type is formed over the voltage sustaining region to define a junction therebetween.

Method for fabricating a power semiconductor device having a voltage sustaining layer with a terraced trench facilitating formation of floating islands

A new and complete description of the current carrying mechanisms of a power MOSFET is presented. This is aimed at clarifying the relatively complex behavior of such devices operating at high current densities, with particular reference to the drain-voltage dependence associated with quasi-saturation. This physical insight provides an elegant method of comparing the relative merits of the DMOS and UMOS structures.

https://ieeexplore.ieee.org/iel1/16/13045/00595944.pdf

The behavior of very high current density power MOSFETs

A trench MOS-gated semiconductor device that includes field relief regions formed below its base region to improve its breakdown voltage, and method for its manufacturing.

Trench mosfet with field relief feature

Silicon carbide (SiC) is a wide-bandgap semiconductor material that has several promising properties for use in power electronics applications. While SiC manufacturing techniques are still being researched, several SiC devices such as SiC Schottky diodes have entered the market and are finding utility in numerous applications. In this paper, a new 1200 V, 10 A SiC MOSFET will be compared to 1000 V, 10 A Si MOSFET in terms of their dc and transient characteristics and their switching performance in a step-down converter. The SiC device compares favorably to the Si device tested as well as other Si devices available on the market for a similar voltage range.

A Comparison of Silicon and Silicon Carbide MOSFET Switching Characteristics

This paper presents a modification to the conventional VDMOS transistor which considerably reduces the effect of quasi-saturation. This modification consists of introducing a deep trench into the structure which is located in the centre of each MOS cell. By extending the gate oxide and metalization into the trench, an accumulation layer is formed deep into the bulk of the device, which modulates the total drift region resistance. A two-dimensional numerical simulator is used to investigate the electrical and thermal performance of the device through which it is shown that the device not only removes the quasi-saturation effect, but also gives lower on-resistance, and much more attractive synchronous rectifying characteristics when compared to the conventional VDMOST structure with an equivalent geometry.

Numerical analysis of a trench VDMOST structure with no quasi-saturation

The quasisaturation behaviour in the high voltage MOSFET structure with a vertical trench gate (UMOS) is studied and demonstrated using 2D numerical simulation techniques. The results show that the quasisaturation effect is mainly due to the conduction area and conductance of the drift region becoming the main constraint at high gate voltage and drain current levels. A simple analytical expression for the quasisaturation current using a simple resistive model is derived and verified based on the simulation results. The effect that the geometry of the trench has on the quasisaturation behaviour is studied, and it is found that increasing the depth and width of the trench improves the quasisaturation operation.

Modelling of the quasisaturation behaviour in the high-voltage MOSFET with vertical trench gate

A voltage-sustaining structure with embedded oppositely doped islands is proposed. Due to the compensation of the field induced by these regions, the doping density of the voltage-sustaining layer can be made larger than that in a conventional voltage-sustaining layer with the same breakdown voltage, and therefore the on-voltage can be reduced. The theory of design for such structures is found to be in good agreement with the results of full 2-dimensional simulation. The on-state performance, the transient behaviour and the potential applications of this structure in power devices are also discussed.

http://ieeexplore.ieee.org/iel5/2190/16993/00785301.pdf

High-voltage sustaining structure with embedded oppositely doped regions

An N-type buffer region is introduced into the N+ source of the IGBT to make it latch-up free. This is done by controlling the resistances of the buffer N region and the P base. A latch-up free condition based on these resistances is presented. 2D numerical simulation is used to demonstrate the concept and the results show that the device can be made to be latch-up free by decreasing the doping concentration of the N-buffer or increasing the doping in the P base in accordance with this condition. Further, a control gate is introduced into the buffer layer to control its resistance, and the simulation results show that latch-up can also be eliminated by applying a sufficiently negative voltage on this gate. Lastly, the effect of the MOS gating level on the latch-up for IGBT is given, and the results are discussed qualitatively.

Design of IGBTs for latch-up free operation

The transient thermal behaviour, based on a rigorous transient thermodynamic treatment, of a power VDMOS transistor during turn‐off is presented. The time variation of the interior lattice temperature within the device is calculated by self‐consistently solving the fully coupled Poisson's equation and transient electron continuity equation together with the transient heat flow equation. The simulation takes account of temperature dependent heat conduction and capacity and includes thermoelectric currents due to temperature gradient. To make the transient thermal simulation more robust, a new analytical expression for heat capacity is used.

M.S. Towers

Papers

Numerical analysis of a trench VDMOST structure with no quasi-saturation

Modelling of the quasisaturation behaviour in the high-voltage MOSFET with vertical trench gate

High-voltage sustaining structure with embedded oppositely doped regions

Design of IGBTs for latch-up free operation

Simulation of transient self-heating during power VDMOS transistor turn-off