Impact of Pocket Layer on Linearity and Analog/RF Performance of InAs-GaSb Vertical Tunnel Field-Effect Transistor

The comprehensive numerical simulation analysis on temperature effects for ferroelectric TFET is proposed in this work. This research demonstrates detailed simulation-based investigation of the volatility of DC parameters such as transfer characteristics, sub-threshold swing (SS), and ION/IOFF ratio throughout a temperature range of 200 K–450 K. In terms of RF figure of merits (FoMs), the proposed design is contrasted with a typical FE-TFET model. The TCAD simulator was also utilized to examine the RF/Analog behavior of the suggested design against temperature. This investigation also looks at how temperature affects voltage intersect points (VIP2 and VIP3), third order power intercept points (IIP3), higher order harmonics (gm2 and gm3), and third order intermodulation distortion (IMD3). Temperature fluctuations on the 1-dB compressive point were used to evaluate the device's linearity. It is found that the Fe-HTFET suggested here is less susceptible to thermal effects than the standard TFETs in our comparison investigation. This shows that the Fe-HTFET presented is more dependable than the traditional TFET in low power applications at extreme temperature. 

Investigation of temperature for the stacked Ferroelectric Heterojunction TFET(Fe-HTFET) on box substrate

Impact of traps on DC, analog/RF, and linearity performance of Ferro-TFET

Spin-dependent Transport Properties of a Tetra-coordinated Fe(II) Spin-crossover Complex

Overcoming bit loss mechanism in self-amplified multilevel silicon-oxide-nitride-oxide-silicon memory cell

We have investigated the characteristics of a hetero-dielectric ferroelectric tunnel (HD-FeTFET). Extensive simulations show that using a hetero-dielectric gate architecture in the lateral direction (non-ferroelectric/ferroelectric/non-ferroelectric) results in more desirable analog/RF characteristics. The proposed structure is compared with conventional tunnel field effect transistors (TFETs) and ferroelectric TFET (FeTFET). Simulation results manifest that HD-FeTFET is superior to other compared structures, and benefits from both ferroelectric and hetero-dielectric structure. Negative capacitance effect in ferroelectric causes a step-up voltage transformer, as a result the subthreshold swing decreases. Owing to two different dielectric constants in the hetero-dielectric structure, the electric field enhances; thereby, the on-state current increases. In this paper, important analog/RF figures of merit, such as cut-off frequency (fT), maximum oscillation frequency (fmax), transconductance frequency product, and intrinsic time delay (τ), are investigated. Also, linearity parameters including VIP2, VIP3, IIP3, and the 1-dB compression point are considered. We achieve average sub-threshold swing of 14 mV for 5 decades for HD-FeTFET, and is improved by ∼ 48% and ∼ 30% for TFET and FeTFET, respectively. Moreover, the ION/IOFF ratio and the on-state current for the proposed structure are 1011 and 5.3 × 10−7 (A/μm), respectively.

Impact of Hetero-Dielectric Ferroelectric Gate Stack on Analog/RF Performance of Tunnel FET

The prominent method used for altering the negative differential resistance (NDR) of nanoribbon devices is changing nanoribbon structures, which complicates the design and fabrication process. To solve such problems, for the first time, the present study proposes a novel and tunable method – Multiple-Gate Method (MGM) – for the NDR engineering of nanoribbon devices. Following a universal logic, MGM can be applied to all types of nanoribbon materials. Substantially, it can be applied to bulk devices by taking into account proper considerations. At the beginning of the paper, novel structures based on defect engineering of nanoribbons are presented for the NDR engineering of Phosphorene Nanoribbons (PNR) due to the lack of research on this domain of this new material. Then, the multiple-gate method is proposed for the NDR engineering of the PNRs as an alternative to defect engineering.

Malihe Zare

Papers

Impact of Hetero-Dielectric Ferroelectric Gate Stack on Analog/RF Performance of Tunnel FET

A novel universal tunable method for the NDR engineering of nanoribbon devices; the defect engineering of PNR devices

A New and Tunable Method for the Ndr Engineering of Nanoribbon Materials and Devices

An analytical charge-based capacitance model for double-gate tunnel FETs

N-terminal truncation of peptide effects on human serum albumin and beta amyloid peptide interaction