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M

Marco G. Pala

Researcher at Université Paris-Saclay

Publications -  122
Citations -  2232

Marco G. Pala is an academic researcher from Université Paris-Saclay. The author has contributed to research in topics: Nanowire & Quantum tunnelling. The author has an hindex of 27, co-authored 111 publications receiving 1978 citations. Previous affiliations of Marco G. Pala include University of Pisa & Centre national de la recherche scientifique.

Papers
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Phonon- and surface-roughness-limited mobility of gate-all-around 3C-SiC and Si nanowire FETs.

TL;DR: Numerical simulations of gate-all-around (GAA) 3C-SiC and Si nanowire (NW) field effect transistors (FETs) using a full quantum self-consistent Poisson-Schrödinger algorithm within the non-equilibrium Green's function (NEGF) formalism imply that the difference between Si and 3C -SiC device mobility is reduced at large gate voltages.
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Surface-Roughness-Induced Variability in Nanowire InAs Tunnel FETs

TL;DR: In this article, a 3D full-quantum approach based on the Non-Equilibrium Green's Function formalism is proposed to study the surfaceroughness (SR)-induced variability at low supply voltage VDD = 0.3 V in nanowire InAs tunnel FETs and strained-silicon (sSi) MOSFETs.
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Local density of states in mesoscopic samples from scanning gate microscopy

TL;DR: In this paper, the relationship between the local density of states (LDOS) and the conductance variation Delta G in scanning-gate-microscopy experiments on mesoscopic structures as a charged tip scans above the sample surface was studied.
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Nonlocal Andreev transport through an interacting quantum dot

TL;DR: In this article, the authors investigate subgap transport through a single-level quantum dot tunnel coupled to one superconducting and two normal-conducting leads, and propose two schemes to identify nonlocal Andreev transport.
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Channel-Length Dependence of Low-Field Mobility in Silicon-Nanowire FETs

TL;DR: In this article, the role of two main scattering mechanisms responsible for mobility degradation in ultrashort electron devices like silicon-nanowire FETs was investigated, and electron-phonon interaction and surface roughness (SR) at the Si/SiO2 interface were considered as sources of inelastic and elastic scatterings.