M
Mark E. Mason
Researcher at Texas Instruments
Publications - 31
Citations - 199
Mark E. Mason is an academic researcher from Texas Instruments. The author has contributed to research in topics: Design for manufacturability & Optical proximity correction. The author has an hindex of 8, co-authored 31 publications receiving 195 citations.
Papers
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Proceedings ArticleDOI
A shallow trench isolation study for 0.25/0.18 /spl mu/m CMOS technologies and beyond
Amitava Chatterjee,J. Esquivel,Somnath S. Nag,Iqbal Ali,D. Rogers,Keith A. Joyner,Mark E. Mason,Doug Mercer,A. Amerasekera,Theodore W. Houston,Ih-Chin Chen +10 more
TL;DR: In this paper, a manufacturable shallow trench isolation (STI) technology using high density plasma (HDP) CVD oxide as trench filling material is reported for the first time, and compared to using sub-atmospheric CVD (SACVD) oxide as filling material.
Journal ArticleDOI
Integration of unit processes in a shallow trench isolation module for a 0.25 μm complementary metal–oxide semiconductor technology
Amitava Chatterjee,Iqbal Ali,Keith A. Joyner,Doug Mercer,John Kuehne,Mark E. Mason,A. L. Esquivel,D. Rogers,Sean C. O'Brien,P. Mei,S. Murtaza,S. P. Kwok,Kelly J. Taylor,Somnath S. Nag,G. Hames,Maureen A. Hanratty,H. Marchman,S. Ashburn,I.-C. Chen +18 more
TL;DR: In this paper, a shallow trench isolation (STI) flow suitable for 0.25 μm complementary metal-oxide semiconductor technologies is proposed and the issues in integrating the pattern, fill, planarization, and surface cleanup processes to design a STI flow are discussed.
Proceedings ArticleDOI
65nm node gate pattern using attenuated phase shift mask with off-axis illumination and sub-resolution assist features
Gary Zhang,Mark Terry,Sean C. O'Brien,Robert A. Soper,Mark E. Mason,Won D. Kim,Changan Wang,Steven G. Hansen,Jason Lee,Joe Ganeshan +9 more
TL;DR: Gate pattern capabilities in terms of DOF, exposure latitude, mask error enhancement factor (MEEF), optical proximity correction (OPC), CD control, and aberration sensitivity are reported in this paper.
Design for Manufacturability through Design-Process Integration VII
Mark E. Mason,John L. Sturtevant +1 more
Patent
Test Method and System for Characterizing and/or Refining an IC Design Cycle
TL;DR: In this paper, a set of at least one of the plurality of non-critical paths is modified to produce a modified design in which the sensitivity of each of the set of noncritical paths to each parameter is enhanced.