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Masahiro Ushiyama

Researcher at Hitachi

Publications -  21
Citations -  263

Masahiro Ushiyama is an academic researcher from Hitachi. The author has contributed to research in topics: Silicon oxide & Layer (electronics). The author has an hindex of 8, co-authored 21 publications receiving 263 citations. Previous affiliations of Masahiro Ushiyama include HGST.

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Patent

Manufacturing method of non-volatile semiconductor memory device

TL;DR: In this article, the interlayer insulating film of a nonvolatile memory is selectively removed on the peripheral circuit MOS area, and the polycrystalline silicon film as a lower layer is used as a buffer layer against contamination or damage due to the etching.
Patent

Semiconductor device having thin electrode layer adjacent gate insulator and method of manufacture

TL;DR: In this paper, a nonvolatile semiconductor memory device is described, which includes a gate electrode (e.g., floating gate electrode) having a first layer of an amorphous silicon film, or a polycrystalline silicon thin film or a film of a combination of ammorphous and polycrystaline silicon, on the gate insulating film.
Patent

Semiconductor device and production method thereof

TL;DR: In this paper, a gate dielectric film 6 is made as follows: after forming a silicon nitride film 3 with a specified thickness, it is annealed in an oxidizing atmosphere to form silicon oxide 4 on the silicon oxide film 3, then this silicon oxide is completely removed by exposure to a dissolving liquid.
Journal ArticleDOI

An 80 ns 1 Mb flash memory with on-chip erase/erase-verify controller

TL;DR: An internal erase and erase-verify control system implemented in all electrically erasable, reprogrammable, 80-ns, 1-Mb flash memory suitable for in-system reprogram applications is discussed, and timing in the electrical erase mode is shown.
Proceedings ArticleDOI

Two dimensionally inhomogeneous structure at gate electrode/gate insulator interface causing Fowler-Nordheim current deviation in nonvolatile memory

TL;DR: In this article, the gate electrode polycrystalline silicon (gate poly-Si)/gate insulator SiO/sub 2/ interface structure has been studied for obtaining reliable nonvolatile memory devices.