Wide-band-gap oxides such as SrTiO3 are shown to be critical tests of theories of Schottky barrier heights based on metal-induced gap states and charge neutrality levels. This theory is reviewed and used to calculate the Schottky barrier heights and band offsets for many important high dielectric constant oxides on Pt and Si. Good agreement with experiment is found for barrier heights. The band offsets for electrons on Si are found to be small for many key oxides such as SrTiO3 and Ta2O5 which limit their utility as gate oxides in future silicon field effect transistors. The calculations are extended to screen other proposed oxides such as BaZrO3. ZrO2, HfO2, La2O3, Y2O3, HfSiO4, and ZrSiO4. Predictions are also given for barrier heights of the ferroelectric oxides Pb1−xZrxTiO3 and SrBi2Ta2O9 which are used in nonvolatile memories.

Band offsets of wide-band-gap oxides and implications for future electronic devices

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

The outstanding properties of SiO2, which include high resistivity, excellent dielectric strength, a large band gap, a high melting point, and a native, low defect density interface with Si, are in large part responsible for enabling the microelectronics revolution. The Si/SiO2 interface, which forms the heart of the modern metal–oxide–semiconductor field effect transistor, the building block of the integrated circuit, is arguably the worlds most economically and technologically important materials interface. This article summarizes recent progress and current scientific understanding of ultrathin (<4 nm) SiO2 and Si–O–N (silicon oxynitride) gate dielectrics on Si based devices. We will emphasize an understanding of the limits of these gate dielectrics, i.e., how their continuously shrinking thickness, dictated by integrated circuit device scaling, results in physical and electrical property changes that impose limits on their usefulness. We observe, in conclusion, that although Si microelectronic devices...

Ultrathin (<4 nm) SiO2 and Si-O-N gate dielectric layers for silicon microelectronics: Understanding the processing, structure, and physical and electrical limits

Journal of Scientific Instruments Editor: Dr H R Lang Vol 28 and Supplement No 1, 1951 Pp xvi + 388 + iii + 80 (London: Institute of Physics, 1951) Bound, £3 12s; unbound, £3

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A Review of Scientific Instruments

This paper reviews the present knowledge on tantalum pentoxide (Ta 2 O 5 ) thin films and their applications in the field of microelectronics and integrated microtechnologies. Different methods used to produce tantalum oxide layers are described, emphazing elaboration mechanisms and key parameters for each technique. We also review recent advances in the deposition of Ta 2 O 5 in the particular field of microelectronics where high quality layers are required from the structural and electrical points of view. The physical, structural, optical, chemical and electrical properties of tantalum oxide thin films on semiconductors are then presented and essential film parameters, such as optical index, film density or dielectric permittivity, are discussed. After a reminder of the basic mechanisms that control the bulk electrical conduction in insulating films, we carefully examine the origin of leakage currents in Ta 2 O 5 and present the state-of-the-art concerning the insulating behaviour of tantalum oxide layers. Finally, applications of tantalum oxide thin films are presented in the last part of this paper. We show how Ta 2 O 5 has been employed as an antireflection coating, insulating layer, gate oxide, corrosion resistant material, and sensitive layer in a wide variety of components, circuits and sensors.

Tantalum pentoxide (Ta2O5) thin films for advanced dielectric applications

A technique is presented for incorporating fluorine (F) into the gate-oxide film, and the subsequent improvement of channel-hot-electron hardness of the resulting MOSFET is reported. This technique uses low-energy F implantation onto the surface of the polysilicon gate-electrode, followed by annealing at 950 degrees C to diffuse F into the gate SiO/sub 2/ toward the SiO/sub 2//Si interface. The improved hot-electron hardness is explained by a model involving a strain relaxation near the SiO/sub 2//Si interface by fluorine incorporation that results from Si-F bond formation. >

Hot-electron hardened Si-gate MOSFET utilizing F implantation

Before a high permittivity interlayer insulating film of a non-volatile memory having a two-level gate electrode structure, a surface of a substrate in a peripheral circuit MOS area is successively covered with a thermal oxide film and a polycrystalline silicon film. Before the interlayer insulating film is selectively removed on the peripheral circuit MOS area, the surface of the interlayer insulating film of the non-volatile memory is covered with a polycrystalline silicon film. When the interlayer insulating film in the peripheral circuit MOS area is removed, the polycrystalline silicon film as a lower layer in the peripheral circuit area serves as a buffer layer against contamination or damage due to the etching, and the conductive layer on the surface of the interlayer insulating film in the non-volatile memory portion also serves as a buffer layer against the contamination or damage due to the etching.

Manufacturing method of non-volatile semiconductor memory device

With recent decreases in the size of semiconductor memories, isolation problems typically arise during fabrication of a capacitor for a high-capacity semiconductor memory device. To overcome this, arrangements are provided to improve the isolation between capacitor elements even if those elements are extremely close together. For example, if a material such as platinum is used as a capacitor bottom electrode, a thin layer of titanium oxide can be deposited before forming the platinum, to provide a structure in which the titanium oxide is on the bottom portion of the trench. A high-dielectric-constant insulator is then formed over that structure by the Chemical Vapor Deposition. The high-dielectric-constant insulator has a composition which satisfies the stoichiometric composition over the platinum and which has more titanium atoms than those of the stoichiometric composition on the trench bottom. The resulting non-stoichiometric composition layer formed on the trench bottom has a low dielectric constant and a high insulation to maintain electric insulation between adjoining bottom capacitor electrodes. Because of a low crystallization, moreover, a layer having a planarized morphology is formed.

Semiconductor memory device having improved isolation between electrodes, and process for fabricating the same

Improvement of dielectric breakdown characteristics and hot‐electron‐induced interface degradation of metal‐oxide‐semiconductor capacitors having fluorinated ultradry oxides has been demonstrated. The fluorine is introduced through HF surface treatment of Si prior to oxidation. Secondary‐ion mass spectrometry data indicate that SiF distribution is peaked both at the surface of the oxide and at the SiO2/Si interface in the fluorinated ultradry oxide. The possible role of fluorine on the improvement of the dielectric characteristics will be discussed.

Dielectric characteristics of fluorinated ultradry SiO2

We have investigated the controllability of the effective work function (phim,eff) of TiN as a work-function-determining metal (WFM) for various gate-electrode structures in HfSiON MOSFETs. phim,eff was controllable from 4.7 to 4.44 eV by changing the TiN thickness from 30 to 2 nm in poly-Si/TiN gate electrodes, without any distinct increase in EOT. Therefore, thin-TiN and thick-TiN WFMs are preferred for the reduction in threshold voltage in nMOSFETs and pMOSFETs with poly-Si/TiN gate electrodes, respectively. A similar controllability was not observed with W/TiN gate electrodes but was evident with W/TaSiN/TiN gate electrodes. This means that controllability is a characteristic of metal gate electrodes with a structure including a Si-rich layer (such as poly-Si and TaSiN)/TiN. It is considered that Ti suboxides, which increase phim,eff as a thin insulator with negative fixed charges, or interface dipoles in the TiN/HfSiON interface, are reduced by oxidation of the Si-rich layer, producing the required result of phim,eff decrease when the TiN thickness becomes as thin as 2 nm.

Yuzuru Ohji

Papers

Hot-electron hardened Si-gate MOSFET utilizing F implantation

Manufacturing method of non-volatile semiconductor memory device

Semiconductor memory device having improved isolation between electrodes, and process for fabricating the same

Dielectric characteristics of fluorinated ultradry SiO2

Effective-Work-Function Control by Varying the TiN Thickness in Poly-Si/TiN Gate Electrodes for Scaled High- $k$ CMOSFETs