Showing papers by "Matteo Sonza Reorda published in 1995"

Industrial BIST of embedded RAMs

Abstract: High-quality memory testing is increasingly important, especially when RAMs and ROMs are deeply embedded in bigger systems, as the techniques based on control and observation points fail. Adopting a built-in self-test scheme for deeply embedded memories seems advantageous and industrial experience at Italtel, a telecom company, confirms it. The scheme implements in hardware the test pattern generation algorithm proposed by R. Nair, S.M. Thatte, and J.A. Abraham \cite{NTAb78}, extending it to word-based memories. Area overhead, performance degradation, additional pins, and test time are minimal, whereas we guarantee high fault coverage for the significant failure modes and full testability of the BIST hardware, as the experimental results confirm.

A portable ATPG tool for parallel and distributed systems

Abstract: The use of parallel architectures for the solution of CPU and memory critical problems in the electronic CAD area has been limited up to now by several factors, like the lack of efficient algorithms the reduced portability of the code, and the cost of the hardware. However, portable message-passing libraries are now available, and the same code runs on high-cost supercomputers, as well as on common workstation networks. The paper presents an effective ATPG system for large sequential circuits developed using the PVM library and based on a genetic algorithm. The tool, named GATTO has been run on a DEC Alpha AXP farm and on a CM-5. Experimental results are provided.

A data parallel algorithm for Boolean function manipulation

Abstract: This paper describes a data-parallel algorithm for boolean function manipulation. The algorithm adopts Binary Decision Diagrams (BDDs), which are the state-of-the-art approach for representing and handling boolean functions. The algorithm is well suited for SIMD architectures and is based on distributing BDD nodes to the available Processing Elements and traversing BDDs in a breadth-first manner. An improved version of the same algorithm is also presented, which does not use virtual processors. A prototypical package has been implemented and its behavior has been studied with two different applications. In both cases the results show that the approach exploits well the parallel hardware by effectively distributing the load; thanks to the limited CPU time required and to the great amount of memory available, it can solve problems that can not be faced with by conventional architectures. >

A PVM tool for automatic test generation on parallel and distributed systems

Abstract: The use of parallel architectures for the solution of CPU and memory critical problems in the Electronic CAD area has been limited up to now by several factors, like the lack of efficient algorithms, the reduced portability of the code, and the cost of hardware. However, portable message-passing libraries are now available, and the same code runs on high-cost supercomputers, as well as on common workstation networks. The paper presents an effective ATPG system for large sequential circuits developed using the PVM library and based on a Genetic Algorithm. The tool, named GATTO*, runs on a DEC Alpha AXP farm and a CM-5. Experimental results are provided.

Exploiting massively parallel architectures for the solution of diffusion and propagation problems

Abstract: Many problems in several fields like physics, chemistry, biology and engineering lack an analytical solution able to provide a satisfactory phenomena description. Then a numerical solution becomes the only viable alternative. The use of massively parallel architectures often allows one to obtain in an easy way a comprehensive picture of the behaviour of the solution. We present here a computational model applied to two different physical problems; our work demonstrates the effectiveness of the approach and its extensibility to many classes of problems in different fields.