Showing papers by "Matteo Sonza Reorda published in 2006"

A new hybrid fault detection technique for systems-on-a-chip

Abstract: Hardening SoCs against transient faults requires new techniques able to combine high fault detection capabilities with the usual requirements of SoC design flow, e.g., reduced design-time, low area overhead, and reduced (or null) accessibility to source core descriptions. This paper proposes a new hybrid approach which combines hardening software transformations with the introduction of an Infrastructure IP with reduced memory and performance overheads. The proposed approach targets faults affecting the memory elements storing both the code and the data, independently of their location (inside or outside the processor). Extensive experimental results, including comparisons with previous approaches, are reported, which allow practically evaluating the characteristics of the method in terms of fault detection capabilities and area, memory, and performance overheads.

An Effective Technique for Minimizing the Cost of Processor Software-Based Diagnosis in SoCs

Abstract: The ever increasing usage of microprocessor devices is sustained by a high volume production that in turn requires a high production yield, backed by a controlled process. Fault diagnosis is an integral part of the industrial effort towards these goals. This paper presents a novel cost-effective approach to the construction of diagnostic software-based test sets for microprocessors. The methodology exploits an existing post-production test set, designed for software-based self-test, and an already developed infrastructure IP to perform the diagnosis. An initial diagnostic test set is built, and then iteratively refined resorting to an evolutionary method. Experimental results are reported in the paper showing the feasibility and effectiveness of the approach for an Intel i8051 processor core.

System-in-package testing: problems and solutions

Abstract: System-in-package integrates multiple dies in a common package. Therefore, testing SiP technology is different from system-on-chip, which integrates multiple vendor parts. This article provides test strategies for known good die and known good substrate in the SiP. Case studies prove feasibility using the IEEE 1500 test structure

On the automation of the test flow of complex SoCs

Abstract: Modern systems-on-chip (SoCs) allow integrating many different functional cores in the same piece of silicon. Their test requires taking fast decisions in the selection of structures and strategies at different stages of the design flow: early computation of area overhead, power consumption and test application time are indispensable in order to develop effective and efficient test for the overall chip, while taking into account physical constraints imposed by the available test equipment. Furthermore, once the test strategy has been selected and patterns generated for each module, additional nonnegligible effort is required to integrate the test program in an ATE-readable format. In this paper, we tackle these problems by means of a new software platform, leveraging descriptions of both the core-level test structure and the system-level requirements. Experimental results related to a realistic case of study underline the effectiveness of the tool and its potentialities in the IEEE 1500 environments.

Embedded Memory Diagnosis: An Industrial Workflow

Abstract: Embedded memory modules are sensitive components that deeply influence production yield of integrated devices. For fast yield improvement, an efficient manufacturing test must supply advanced defect characterization that helps in discovering technology weaknesses and finding strategies for improvement. This paper presents an industrial workflow for embedded memory diagnosis. It is based on the integration of March-based diagnostic BIST hardware in an IEEE 1500-compliant environment, and on a novel diagnostic algorithm for determining the fault model associated to the retrieved syndromes. An experimental implementation showing the feasibility of the approach is presented.

Efficient techniques for automatic verification-oriented test set optimization

Abstract: Most Systems-on-a-Chips include a custom microprocessor core, and time and resource constraints make the design of such devices a challenging task. This paper presents a simulation-based methodology for the automatic completion and refinement of verification test sets. The approach extends the µGP, an evolutionary test program generator, with the possibility to enhance existing test sets. Already devised test programs are not merely included in the new set, but assimilated and used as a starting point for a new test-program cultivation task. Reusing existing material cuts down the time required to generate a verification test set during the microprocessor design. Experimental results are reported on a small pipelined microprocessor, and show the effectiveness of the approach. Additionally, the use of the proposed methodology enabled to experimentally analyze the relationship of the different code coverage metrics used in the test program generation.

Early, accurate dependability analysis of CAN-based networked systems

Abstract: Many safety-critical applications today rely on computer-based systems in which several computing nodes communicate through a network backbone. As the complexity of the systems under analysis grows, designers must devise fault-injection models that strike a balance between two conflicting requirements: On the one hand, models should be as close as possible to a system's physical implementation to reflect precisely the effects of real faults. On the other hand, abstract, easily manageable models minimize the time required for the fault-injection experiments, letting designers analyze sets of faults wide enough to provide statistically meaningful information. In addressing this issue, we have devised a fault-injection environment to study the effects of soft errors in CAN networks. Our cosimulation environment consists of two modules. The first, a traffic generator module implemented in software, emulates the applications running in each node of the network. The second, a network backbone module implemented in hardware, simulates the activities involved in information exchange between network nodes, in compliance with the CAN protocol specification. To allow evaluation of complex workloads as well as large fault lists, we use an FPGA board to emulate the network backbone module. This enables cycle-accurate simulations of the entire network's behavior with very low speed penalties.

Hardware-in-the-loop-based dependability analysis of automotive systems

Abstract: Automotive systems embed several electronic control units whose purpose is to help drivers in controlling vehicles, as well as guaranteeing the safety of vehicles' occupants. The occurrence of faults affecting these units can have dramatic impacts, and must be forecasted as earlier as possible during the conception of new vehicles. In this paper we propose a new fault-injection system based on a hardware-in-the-loop vehicle model. The main novelty of our system is the possibility of directly relating fault effects to vehicle's dynamic response without performing long and expensive experiments on a prototype running on a test track.

An Evolutionary Methodology to Enhance Processor Software-Based Diagnosis

Abstract: The widespread use of cheap processor cores requires the ability to quickly point out the manufacturing process criticalities in an effort to enhance the production yield. Fault diagnosis is an integral part of the industrial effort towards these goals. This paper describes an innovative application of evolutionary algorithms: iterative refinement of a diagnostic test set. Several enhancements in the used evolutionary core are additionally outlined, highlighting their relevance for the specific problem. Experimental results are reported in the paper showing the effectiveness of the approach for a widely-known microcontroller core.