Showing papers by "Matteo Sonza Reorda published in 2012"

A new SBST algorithm for testing the register file of VLIW processors

Abstract: Feature size reduction drastically influences permanent faults occurrence in nanometer technology devices. Among the various test techniques, Software-Based Self-Test (SBST) approaches have been demonstrated to be an effective solution for detecting logic defects, although achieving complete fault coverage is a challenging issue due to the functional-based nature of this methodology. When VLIW processors are considered, standard processor-oriented SBST approaches result deficient since not able to cope with most of the failures affecting VLIW multiple parallel domains. In this paper we present a novel SBST algorithm specifically oriented to test the register files of VLIW processors. In particular, our algorithm addresses the cross-bar switch architecture of the VLIW register file by completely covering the intrinsic faults generated between the multiple computational domains. Fault simulation campaigns comparing previously developed methods with our solution demonstrate its effectiveness. The results show that the developed algorithm achieves a 97.12% fault coverage which is about twice better than previously developed SBST algorithms. Further advantages of our solution are the limited overhead in terms of execution cycles and memory occupation.

A New Fault Injection Approach for Testing Network-on-Chips

Abstract: Packet-based on-chip interconnection networks, or Network-on-Chips (NoCs) are progressively replacing global on-chip interconnections in Multi-processor System-on-Chips (MP-SoCs) thanks to better performances and lower power consumption However, modern generations of MP-SoCs have an increasing sensitivity to faults due to the progressive shrinking technology Consequently, in order to evaluate the fault sensitivity in NoC architectures, there is the need of accurate test solution which allows to evaluate the fault tolerance capability of NoCs This paper presents an innovative test architecture based on a dual-processor system which is able to extensively test mesh based NoCs The proposed solution improves previously developed methods since it is based on a NoC physical implementation which allows to investigate the effects induced by several kind of faults thanks to the execution of on-line fault injection within all the network interface and router resources during NoC run-time operations The solution has been physically implemented on an FPGA platform using a NoC emulation model adopting standard communication protocols The obtained results demonstrated the effectiveness of the developed solution in term of testability and diagnostic capabilities and make our solutions suitable for testing large scale NoC design

E-Learning at Politecnico di Torino: Moving to a Sustainable Large-Scale Multi-Channel System of Services

Abstract: Politecnico di Torino has been actively experimenting distance education scenarios since 1992, through the development of innovative methodologies and tools. The real challenge today, however, is to move from small settings to a large-scale system able to suit the needs of a broad number of users belonging to different categories, from traditional students to part-time or full-time workers, from students living far from Torino to people with participation restriction due to disability. The emphasis then, is not only on the innovation of methodologies and technologies, but on their effective and economically sustain- able use in a complex and multi-faceted setting. This chapter describes the services introduced in this direction and gives a preliminary evaluation after the first year of delivery

On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors

Abstract: Software-Based Self-Test (SBST) approaches have shown to be an effective solution to detect permanent faults, both at the end of the production process, and during the operational phase. However, when Very Long Instruction Word (VLIW) processors are addressed these techniques require some optimization steps in order to properly exploit the parallelism intrinsic in these architectures. In this chapter we present a new method that, starting from previously known algorithms, automatically generates an effective test program able to still reach high fault coverage on the VLIW processor under test, while minimizing the test duration and the test code size. Moreover, using this method, a set of small SBST programs can be generated aimed at the diagnosis of the VLIW processor. Experimental results gathered on a case study show the effectiveness of the proposed approach.

On-line test of embedded systems: Which role for functional test?

Abstract: On-line test of embedded systems is becoming increasingly important mainly due to the growing usage of electronic systems in safety-critical applications and to the higher chances of failures in new devices. Standards and regulations are also pushing the adoption of effective on-line test solutions both at the device and at the system level. While Design for On-Line Testability is definitely an effective solution, there are situations in which alternative or complementary ways have to be explored, and functional testing stands as the only viable solution. The presentation will overview the main open issues in this area (e.g., in terms of achievable defect coverage, test time, and costs), emphasizing the limitations of the functional approach, but also reporting about recent advancements that could allow its easier and wider adoption in practice.