Building programmable resistive devices in contact holes at the crossover of a plurality of conductor lines in more than two vertical layers is disclosed. There are plurality of first conductor lines and another plurality of second conductor lines that can be substantially perpendicular to each other, though in two different vertical layers. A diode and/or a programmable resistive element can be fabricated in the contact hole between the first and second conductor lines. The programmable resistive element can be coupled to another programmable resistive device or shared between two programmable devices whose diodes conducting currents in opposite directions and/or coupled to a common conductor line. The programmable resistive memory can be configured to be programmable by applying voltages to conduct current flowing through the programmable resistive element to change its resistance for a different logic state.

Programmable Resistive Device and Memory Using Diode as Selector

Junction diodes or MOS devices fabricated in standard FinFET technologies can be used as program selectors or One-Time Programmable (OTP) element in a programmable resistive device, such as interconnect fuse, contact/via fuse, anti-fuse, or emerging nonvolatile memory such as MRAM, PCRAM, CBRAM, or RRAM. The MOS or diode can be built on at least one fin structure or at least one active region that has at least one first active region and a second active region. The first and the second active regions can be isolated by a dummy MOS gate or silicide block layer (SBL) to construct a diode.

Circuit and system of using FinFET for building programmable resistive devices

A method and system for multiple-bit programmable resistive cells having a multiple-bit programmable resistive element and using diode as program selector are disclosed. The first and second terminals of the diode having a first and second types of dopants can be fabricated from source/drain of MOS in a well for MOS devices or fabricated on the same polysilicon structure. If a multiple-bit programmable resistive cell has 2 n (n>1) distinct resistance levels to store n-bit data, at least 2 n −1 reference resistance levels can be designated to differential resistances between two adjacent states. Programming multiple-bit programmable resistive elements can start by applying a program pulse with initial program voltage (or current) and duration. A read verification cycle can follow to determine if the desirable resistance level is reached. If the desired resistance level has not been reached, additional program pulses can be applied.

Multiple-Bit Programmable Resistive Memory Using Diode as Program Selector

In-system repairing or configuring faulty memories after being used in a system. In one embodiment, a memory chip can include at least one OTP memory to store defective addresses that are to be repaired. The OTP memory can operate without requiring additional I/O pins or high voltage supplies for reading or programming. The memory chip can also include control logic to control reading or programming of the OTP memory as needed.

System and method of in-system repairs or configurations for memories

Junction diodes fabricated in standard CMOS logic processes can be used as program selectors for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The OTP device has an OTP element coupled to a diode in a memory cell. The diode can be constructed by P+ and N+ active regions on an N well as the P and N terminals of the diode. By applying a high voltage to the P terminal of a diode and switching the N terminal of a diode to a low voltage for suitable duration of time, a current flows through an OTP element in series with the program selector may change the resistance state. The P+ active region of the diode can be isolated from the N+ active region in the N well by using dummy MOS gate, SBL, or STI/LOCOS isolations. If the resistive element is an interconnect fuse based on CMOS gate material, the resistive element can be coupled to the P+ active region by an abutted contact such that the element, active region, and metal are connected in a single rectangular contact.

Circuit and system of using junction diode as program selector for one-time programmable devices

A new fully CMOS process compatible anti-fuse device with programmable contact has been developed for advanced programmable logic applications. This anti-fuse processed by pure logic process and decoupled with transistor gate oxide has a highly stable and extremely wide on/off window. It exhibits superior disturb immunity in program and read operations. The device additionally provides the capability to adapt multiple programmable contacts for the needs of elevated data writing and reading performance. This novel anti-fuse cell is a very promising programmable logic solution with fully CMOS logic compatible process below 0.13?m node.

A New CMOS Logic Anti-Fuse Cell with Programmable Contact

A new CMOS-process-compatible programmable contact antifuse (PCAF) cell is presented in this letter for advance programmable logic applications. This innovative PCAF cell adapts an oxide layer formed by the etched resist-protection oxide layer under a properly designed contact region, which results in a highly scalable one-time-programmable solution for advance logic circuits. A subcircuit model describing the - characteristics of the antifuse cell before and after program is developed to facilitate the future PCAF memory macro design.

May-Be Chen

Papers

A New CMOS Logic Anti-Fuse Cell with Programmable Contact

A New Antifuse Cell With Programmable Contact for Advance CMOS Logic Circuits