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Ya-Chin King
Researcher at National Tsing Hua University
Publications - 278
Citations - 4420
Ya-Chin King is an academic researcher from National Tsing Hua University. The author has contributed to research in topics: CMOS & Non-volatile memory. The author has an hindex of 32, co-authored 265 publications receiving 3856 citations. Previous affiliations of Ya-Chin King include TSMC & University of California, Berkeley.
Papers
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Journal ArticleDOI
Charge-trap memory device fabricated by oxidation of Si/sub 1-x/Ge/sub x/
TL;DR: In this article, the authors describe a novel technique of fabricating germanium nanocrystal quasi-nonvolatile memory device, which consists of a metal-oxide-semiconductor field effect transistor (MOSFET) with Ge charge-traps embedded within the gate dielectric.
Journal ArticleDOI
Electromagnetic Energy Harvesting Circuit With Feedforward and Feedback DC–DC PWM Boost Converter for Vibration Power Generator System
TL;DR: In this article, an integrated vibration power generator and energy harvesting circuit with feedback control is presented. But the system consists of a mini EH generator and a highly efficient EH circuit implemented on a minute printed circuit board and a 0.35mum CMOS integrated chip.
Proceedings ArticleDOI
24.1 A 1Mb Multibit ReRAM Computing-In-Memory Macro with 14.6ns Parallel MAC Computing Time for CNN Based AI Edge Processors
Cheng-Xin Xue,Wei-Hao Chen,Je-Syu Liu,Jiafang Li,Wei-Yu Lin,Wei-En Lin,Jing-Hong Wang,Wei-Chen Wei,Ting-Wei Chang,Tung-Cheng Chang,Tsung-Yuan Huang,Hui-Yao Kao,Shih-Ying Wei,Yen-Cheng Chiu,Chun-Ying Lee,Chung-Chuan Lo,Ya-Chin King,Chorng-Jung Lin,Ren-Shuo Liu,Chih-Cheng Hsieh,Kea-Tiong Tang,Meng-Fan Chang +21 more
TL;DR: This work proposes a serial-input non-weighted product (SINWP) structure to optimize the tradeoff between area, tMAC and EMAC, and a down-scaling weighted current translator and positive-negative current- subtractor (PN-ISUB) for short delay, a small offset and a compact read-path area.
Proceedings ArticleDOI
A 65nm 1Mb nonvolatile computing-in-memory ReRAM macro with sub-16ns multiply-and-accumulate for binary DNN AI edge processors
Wei-Hao Chen,K. C. Li,Wei-Yu Lin,K. C. Hsu,Pin-Yi Li,Cheng-Han Yang,Cheng-Xin Xue,En-Yu Yang,Yen-Kai Chen,Yun-Sheng Chang,Tzu-Hsiang Hsu,Ya-Chin King,Chorng-Jung Lin,Ren-Shuo Liu,Chih-Cheng Hsieh,Kea-Tiong Tang,Meng-Fan Chang +16 more
TL;DR: Many artificial intelligence (AI) edge devices use nonvolatile memory (NVM) to store the weights for the neural network (trained off-line on an AI server), and require low-energy and fast I/O accesses.
Journal ArticleDOI
CMOS-integrated memristive non-volatile computing-in-memory for AI edge processors
Wei-Hao Chen,Chunmeng Dou,K. C. Li,Wei-Yu Lin,Pin-Yi Li,Jian-Hao Huang,Jing-Hong Wang,Wei-Chen Wei,Cheng-Xin Xue,Yen-Cheng Chiu,Ya-Chin King,Chorng-Jung Lin,Ren-Shuo Liu,Chih-Cheng Hsieh,Kea-Tiong Tang,Jianhua Yang,Mon-Shu Ho,Meng-Fan Chang +17 more
TL;DR: A fully integrated memristive nvCIM structure that integrates a resistive memory array with control and readout circuits using an established 65 nm foundry CMOS process, can offer high energy efficiency and low latency for Boolean logic and multiply-and-accumulation operations.