Building programmable resistive devices in contact holes at the crossover of a plurality of conductor lines in more than two vertical layers is disclosed. There are plurality of first conductor lines and another plurality of second conductor lines that can be substantially perpendicular to each other, though in two different vertical layers. A diode and/or a programmable resistive element can be fabricated in the contact hole between the first and second conductor lines. The programmable resistive element can be coupled to another programmable resistive device or shared between two programmable devices whose diodes conducting currents in opposite directions and/or coupled to a common conductor line. The programmable resistive memory can be configured to be programmable by applying voltages to conduct current flowing through the programmable resistive element to change its resistance for a different logic state.

Programmable Resistive Device and Memory Using Diode as Selector

Decreasing read cell current (ICELL) has become a major trend in nonvolatile memory (NVM). However, a reduced ICELL leaves the operation of the sense amplifier (SAs) vulnerable to bitline (BL) level offset and SA input offset. Thus, small- ICELL NVMs suffer from slow read speed or low read yield. In this study, we propose a new current-sampling-based SA (CSB-SA) to suppress the offset due to device mismatch, while maintaining tolerance for insufficient precharge time. These features enable CSB-SA to achieve a read speed 6.3 ×-8.1× faster than previous SAs, for sensing 100 nA ICELLs on a 2 K-cell bitline. We fabricated a CMOS-logic-compatible, 90 nm, 512 Kb OTP macro, using the CSB-SA. This OTP macro achieves a random access time of 26 ns for reading sub-200 nA ICELL. Measurements confirm that this 90 nm CSB-SA is also capable of sub-100 nA sensing.

An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory

Junction diodes or MOS devices fabricated in standard FinFET technologies can be used as program selectors or One-Time Programmable (OTP) element in a programmable resistive device, such as interconnect fuse, contact/via fuse, anti-fuse, or emerging nonvolatile memory such as MRAM, PCRAM, CBRAM, or RRAM. The MOS or diode can be built on at least one fin structure or at least one active region that has at least one first active region and a second active region. The first and the second active regions can be isolated by a dummy MOS gate or silicide block layer (SBL) to construct a diode.

Circuit and system of using FinFET for building programmable resistive devices

A method and system for multiple-bit programmable resistive cells having a multiple-bit programmable resistive element and using diode as program selector are disclosed. The first and second terminals of the diode having a first and second types of dopants can be fabricated from source/drain of MOS in a well for MOS devices or fabricated on the same polysilicon structure. If a multiple-bit programmable resistive cell has 2 n (n>1) distinct resistance levels to store n-bit data, at least 2 n −1 reference resistance levels can be designated to differential resistances between two adjacent states. Programming multiple-bit programmable resistive elements can start by applying a program pulse with initial program voltage (or current) and duration. A read verification cycle can follow to determine if the desirable resistance level is reached. If the desired resistance level has not been reached, additional program pulses can be applied.

Multiple-Bit Programmable Resistive Memory Using Diode as Program Selector

In-system repairing or configuring faulty memories after being used in a system. In one embodiment, a memory chip can include at least one OTP memory to store defective addresses that are to be repaired. The OTP memory can operate without requiring additional I/O pins or high voltage supplies for reading or programming. The memory chip can also include control logic to control reading or programming of the OTP memory as needed.

System and method of in-system repairs or configurations for memories

A new fully CMOS process compatible anti-fuse device with programmable contact has been developed for advanced programmable logic applications. This anti-fuse processed by pure logic process and decoupled with transistor gate oxide has a highly stable and extremely wide on/off window. It exhibits superior disturb immunity in program and read operations. The device additionally provides the capability to adapt multiple programmable contacts for the needs of elevated data writing and reading performance. This novel anti-fuse cell is a very promising programmable logic solution with fully CMOS logic compatible process below 0.13?m node.

A New CMOS Logic Anti-Fuse Cell with Programmable Contact

A new 45 nm multiple time programming (MTP) cell with self-aligned nitride storage node has been proposed for logic NVM applications. The CMOS fully logic compatible cell has been successfully demonstrated in 45 nm CMOS technology with an ultra small cell size of 0.14 mum2. This cell adapting source side injection programming scheme has a wide on/off window and superior program efficiency. And it also exhibits excellent data retention capability even when logic gate oxide is less than 20 Aring with 45 nm gate length. This new cell provides a promising solution for logic NVM beyond 90 nm node.

A New Self-Aligned Nitride MTP Cell with 45nm CMOS Fully Compatible Process

A new gateless anti-fuse cell with 45 nm CMOS fully compatible process has been developed for advanced programmable logic applications. This gateless anti-fuse cell processed by pure logic process and decoupled with logic gate oxide has a highly stable and five orders of on/off current window. It also exhibits superior program performance by only 5 V operation with no more than 10 muA programming current. This new nitride gateless anti-fuse cell is a very promising logic OTP solution with fully CMOS compatible process below 90 nm node.

45nm Gateless Anti-Fuse Cell with CMOS Fully Compatible Process

A new p-channel nitride-based one-time programmable (OTP) memory was developed for advanced-logic nonvolatile-memory (NVM) applications. A 0.296-mum2/bit (~35 F2) OTP cell, i.e., 0.592 mum2/cell, with a self-aligned nitride storage node was fabricated using standard 90-nm CMOS processes and is fully independent of gate oxide for high scalability. Additionally, the ultrahigh-density OTP cell exhibits excellent retention, immunity against disturbance, and a wide on/off window under the band-to-band hot electron programming. In summary, the new p-channel OTP cell is a very promising solution for use in high-density logic NVM applications beyond the 90-nm technology node.

A Novel 2-Bit/Cell p-Channel Logic Programmable Cell With Pure 90-nm CMOS Technology

In this paper, the effects of large-tilted-angle p-pocket (LAP) implantation on the performance and reliability of stacked-gate memory cell are investigated. The utilization of LAP process achieves the improved programming efficiency and reduced punchthrough susceptibility. The 45° LAP cell featuring a fastest programming speed, however, would not be desirable due to the seriously aggravated read current degradation, drain/read disturbance, and early snap-back breakdown. The cells with 0° and 30° tilted angle are the feasible cells with the moderate programming performance and acceptable reliability constraints. Furthermore, the 0° LAP cell is preferred for the fact that it exhibits the desirable read current than that in 30° cell. Based on the cell performance and reliability consideration, the 0° p-pocket implanted cell is the optimal angle among 0°, 30° and 45° for the future scaling of stacked-gate memory cell.

Hsin-Ming Chen

Papers

A New CMOS Logic Anti-Fuse Cell with Programmable Contact

A New Self-Aligned Nitride MTP Cell with 45nm CMOS Fully Compatible Process

45nm Gateless Anti-Fuse Cell with CMOS Fully Compatible Process

A Novel 2-Bit/Cell p-Channel Logic Programmable Cell With Pure 90-nm CMOS Technology

Performance and Reliability Trade-off of Large-Tilted-Angle Implant P-Pocket on Stacked-Gate Memory Devices