Devices such as keyboards and touchscreens allow humans to communicate with machines. Neural interfaces, which can provide a direct, electrical bridge between analogue nervous systems and digital man-made systems, could provide a more efficient route to future information exchange. Here we review the development of electronic neural interfaces. The interfaces typically consist of three modules — a tissue interface, a sensing interface, and a neural signal processing unit — and based on technical milestones in the development of the electronic sensing interface, we group and analyse the interfaces in four generations: the patch clamp technique, multi-channel neural interfaces, implantable/wearable neural interfaces and integrated neural interfaces. We also consider key circuit and system challenges in the design of neural interfaces and explore the opportunities that arise with the latest technology This Review Article examines the development of neural interfaces, which can provide a direct, electrical bridge between analogue human nervous systems and digital man-made devices, considering challenges and opportunities created with such technology.

Electronic neural interfaces

In many sensor applications, a high-resolution analog-to-digital converter (ADC) is a key block. The use of an incremental delta-sigma ADC (IADC) is often well suited for such applications. While the energy-efficiency of IADCs has improved by several orders of magnitude over the past decade, the implementation of high performance IADCs, especially in battery-powered systems, is still challenging. This paper presents a tutorial review on energy-efficient IADCs and addresses the progress in this area. This paper describes the fundamentals of IADCs and energy-efficient hybrid IADC architectures. Various design techniques for improving the energy-efficiency of the IADCs are described. This paper is intended to serve as a starting point for the development of a new energy-efficient IADC.

Incremental Delta-Sigma ADCs: A Tutorial Review

This article presents the integration of a 32-channel neuromodulation system on chip (SoC) that is developed for chronic implantation in humans. The application-specific integrated circuit (ASIC) offers low-noise recording, a state-of-the-art (SotA) neurostimulator capable of both current- and voltage-controlled stimulation with high-voltage compliance, on-chip 16-bit data digitization as well as safety features such as electrode impedance estimation and charge balancing. The chip communicates through two distinct SPI interfaces for independent command and data transfer. Thus, the developed system constitutes a fully digital, bidirectional 32-channel interface to the brain.

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A High-Voltage Compliance, 32-Channel Digitally Interfaced Neuromodulation System on Chip

Modern neuromodulation systems typically provide a large number of recording and stimulation channels, which reduces the available power and area budget per channel. To maintain the necessary input-referred noise performance despite growingly rigorous area constraints, chopped neural front-ends are often the modality of choice, as chopper-stabilization allows to simultaneously improve (1/f) noise and area consumption. The resulting issue of a drastically reduced input impedance has been addressed in prior art by impedance boosters based on voltage buffers at the input. These buffers precharge the large input capacitors, reduce the charge drawn from the electrodes and effectively boost the input impedance. Offset on these buffers directly translates into charge-transfer to the electrodes, which can accelerate electrode aging. To tackle this issue, a voltage buffer with ultra-low time-averaged offset is proposed, which cancels offset by periodic reconfiguration, thereby minimizing unintended charge transfer. This article explains the background and circuit design in detail and presents measurement results of a prototype implemented in a 180 nm HV CMOS process. The measurements confirm that signal-independent, buffer offset induced charge transfer occurs and can be mitigated by the presented buffer reconfiguration without adversely affecting the operation of the input impedance booster. The presented neural recorder front-end achieves state of the art performance with an area consumption of ${0.036}\,{{\rm {mm}}^2}$ , an input referred noise of ${1.32}\,\mu {\rm {V}}_{\text{rms}}$ (1 to 200 Hz) and ${3.36}\,\mu {\rm {V}}_{\text{rms}}$ (0.2 to 10 kHz), power consumption of ${13.7}\,{\mu {\rm W}}$ from 1.8 V supply, as well as CMRR and PSRR $\ge$ 83 dB at 50 Hz.

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A Chopped Neural Front-End Featuring Input Impedance Boosting With Suppressed Offset-Induced Charge Transfer

This letter presents a neuromodulator frontend that features a reconfigurable current and voltage mode stimulator for a bidirectional, neural interface. By implementing a capacitive high voltage (HV) to low voltage (LV) converter, a single-bit quantizer in the LV domain can be used to compare the difference between the electrode potential and the output of a 7-bit digital-to-analog converter. The digitized signal is integrated to generate a digital feedback signal, which controls a constant current stimulator in order to generate the desired output voltage by adjusting the output current. Thereby the stimulator can deliver up to ±10 mA of output current and ±6 V of stimulation voltage. The stimulation unit is connected over HV protection switches to a neural recorder that features a tunable high-pass cut-off frequency and impulse-based bioimpedance estimation, to form a bidirectional channel. The total consumed silicon area of the frontend is 0.45 mm2 for recording and stimulation. In standby mode the stimulator can be completely disconnected from its biasing, which leads to a power consumption of less than 1 ${\mu }\text{W}$ . The class-B operation during voltage stimulation yields an active power consumption, which is dominated by the stimulator output current in both voltage and current mode.

A Neuromodulator Frontend With Reconfigurable Class-B Current and Voltage Controlled Stimulator

Nyquist-rate ADCs with high resolution are needed in many applications where, for example, multiplexed operation is needed as for multichannel sensor readout. For various tasks such as averaging-based analysis or lock-in detection high linearity at the presence of very low noise is required. While SAR ADCs are known for high power efficiency, they often show limited effective resolutions and linearity unless oversampling, mismatch error shaping or calibration techniques are employed [1,2]. The state of the art in high-resolution ADC design is thus dominated by oversampled converters, and for Nyquist-rate operation a significant power penalty must be paid.

A 1.1mW 200kS/s incremental ΔΣ ADC with a DR of 91.5dB using integrator slicing for dynamic power reduction

This paper presents an improved, bi-directional neural interface with a tunable lower cut-off frequency and an online electrode impedance estimation. Each channel features a low voltage (LV) recorder and a high voltage (HV) stimulator, separated by a HV protection network. The recorder utilizes a 3-Bit switched capacitor (SC), serial DAC to adjust the resistance of a MOS-bipolar pseudo-resistor in the neural recorder. Thereby, its lower cut-off frequency can be adjusted between 15mHz and 70 Hz, with a logarithmic scaling. Additionally a low-gain mode is implemented which together with the HV stimulator allows for an estimation of the electrode impulse response. From this impulse response the parameters of a simplified electrode model can be calculated, with a simulated accuracy of ±15%. A single channel prototype has been layouted and is currently manufactured in a 180 nm HV CMOS technology. The prototype occupies an area of 715 μm × 580 μm. It has a simulated power consumption of 58 μW per channel of which 11 μW are consumed in the tunable Low Noise Amplifier (LNA). The simulated, input referred noise of the LNA ranges between 3.2 μVrms (70 Hz–7.5 kHz) and 4.5 μVrms (0.1 Hz–7.5 kHz) depending on the adjusted value of the lower cut-off frequency.

A bidirectional neural interface featuring a tunable recorder and electrode impedance estimation

This paper presents a dynamic power reduction technique for incremental $\Delta \Sigma $ (I- $\Delta \Sigma $ ) modulators. The technique makes use of the unequal weighting of the digital reconstruction filter. The underlying idea is that the input signal samples are not equally weighted in the higher order reconstruction filter. Thus, it is possible to increase the non-idealities of the I- $\Delta \Sigma $ modulator during the runtime of a single Nyquist conversion, thereby saving power. This principal idea is verified by an example design, where the input-referred noise of the first integrator is dynamically increased, which allows for improved efficiency. The proposed technique is readily applicable to every state-of-the-art I- $\Delta \Sigma $ modulator. Furthermore, it is shown that this property can also be used to switch a single-bit digital-to-analog converter (DAC) into a multibit DAC during runtime, thereby greatly improving the achievable signal-to-quantization-noise ratio (SQNR) without suffering from the DAC non-linearity. The prototype I- $\Delta \Sigma $ modulator is manufactured in a 180-nm CMOS technology and achieves a dynamic range/SNDR = 91.5/86.6 dB for a sampling rate of 200 kS/s while consuming l.l mW from a 3-V supply, while the dynamic power reduction method accounts for 30% power savings.

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Michael Haas

Papers

A High-Voltage Compliance, 32-Channel Digitally Interfaced Neuromodulation System on Chip

A 1.1mW 200kS/s incremental ΔΣ ADC with a DR of 91.5dB using integrator slicing for dynamic power reduction

A Neuromodulator Frontend With Reconfigurable Class-B Current and Voltage Controlled Stimulator

A bidirectional neural interface featuring a tunable recorder and electrode impedance estimation

A Dynamic Power Reduction Technique for Incremental $\Delta\Sigma$ Modulators