Proceedings ArticleDOI
A bidirectional neural interface featuring a tunable recorder and electrode impedance estimation
Michael Haas,Jens Anders,Maurits Ortmanns +2 more
- pp 372-375
TLDR
An improved, bi-directional neural interface with a tunable lower cut-off frequency and an online electrode impedance estimation and the parameters of a simplified electrode model can be calculated, with a simulated accuracy of ±15%.Abstract:
This paper presents an improved, bi-directional neural interface with a tunable lower cut-off frequency and an online electrode impedance estimation. Each channel features a low voltage (LV) recorder and a high voltage (HV) stimulator, separated by a HV protection network. The recorder utilizes a 3-Bit switched capacitor (SC), serial DAC to adjust the resistance of a MOS-bipolar pseudo-resistor in the neural recorder. Thereby, its lower cut-off frequency can be adjusted between 15mHz and 70 Hz, with a logarithmic scaling. Additionally a low-gain mode is implemented which together with the HV stimulator allows for an estimation of the electrode impulse response. From this impulse response the parameters of a simplified electrode model can be calculated, with a simulated accuracy of ±15%. A single channel prototype has been layouted and is currently manufactured in a 180 nm HV CMOS technology. The prototype occupies an area of 715 μm × 580 μm. It has a simulated power consumption of 58 μW per channel of which 11 μW are consumed in the tunable Low Noise Amplifier (LNA). The simulated, input referred noise of the LNA ranges between 3.2 μVrms (70 Hz–7.5 kHz) and 4.5 μVrms (0.1 Hz–7.5 kHz) depending on the adjusted value of the lower cut-off frequency.read more
Citations
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A High-Voltage Compliance, 32-Channel Digitally Interfaced Neuromodulation System on Chip
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A Neuromodulator Frontend With Reconfigurable Class-B Current and Voltage Controlled Stimulator
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A Dynamic Power Reduction Technique for Incremental $\Delta\Sigma$ Modulators
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FIR DACs in CT Incremental Delta-Sigma Modulators
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A 14b, Twofold Time-Interleaved Incremental ΔΣ ADC Using Hardware Sharing
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