Showing papers by "Michael Niemier published in 2012"

Shape Engineering for Controlled Switching With Nanomagnet Logic

Abstract: We demonstrate that in circuits and systems that comprised of nanoscale magnets, magnet-shape-dependent switching properties can be used to perform Boolean logic. More specifically, by making magnets with slanted edges, we can shift the energy barrier of the device (i.e., so that it is not at a maximum when a device is magnetized along its geometrically hard axis). In clocked systems, we can leverage this barrier shift to make and or or gates that are not majority based. Advantages include reduced gate footprint and interconnect overhead as we eliminate one gate input. In this paper, we report and discuss micromagnetic simulations that illustrate how magnet shape can facilitate nonmajority-gate-based, reduced footprint logic; preliminary fabrication and testing results that illustrate that shape engineering can induce energy barrier shifts; and additional micromagnetic simulations that show other ways in which we might leverage shape in circuits made from nanoscale magnets.

On-Chip Clocking of Nanomagnet Logic Lines and Gates

Abstract: The nanomagnet logic (NML) devices considered here are variants of proposed components for the edge-driven, quantum-dot cellular automata device architecture, where the position of electrons on quantum dots was suggested as a mechanism for representing binary state. To control NML circuit components (e.g., gates and lines), to date, externally generated magnetic fields have served as a clock. The clock is used to make the magnets in a circuit ensemble transition to a metastable state, so fringing fields from individual devices can set the state of a neighboring device in accordance with a new input. However, such a clocking scheme is obviously not extensible to chip-level systems. For NML to be a viable candidate for digital systems, a mechanism for simultaneously modulating the energy barriers of a group of devices must be implemented “on-chip,” and guarantee unidirectional dataflow from circuit input to circuit output. We have experimentally demonstrated a CMOS-compatible clock, and used it to reevaluate all of the NML constructs required for a functionally complete logic set. All possible input combinations to said constructs were successfully considered. Experiments were designed to promote unidirectional dataflow.

Switching behavior of lithographically fabricated nanomagnets for logic applications

Abstract: The switching behavior and the magnetization states of non-interacting Supermalloy (Ni79Fe16Mo5) nanomagnet arrays were studied by magnetic measurements and micromagnetic simulations. The switching-field distribution of the easy-axis hysteresis loop of the nanomagnets was broadened due to lithographic shape variations and thermal fluctuations. When cooled to a low temperature (100 K), the switching-field distribution of the loop was reduced and its squareness ratio became higher. We found strong remanent magnetization along the hard axes of the nanomagnets, indicating the presence of metastable states and end-domain states. An oscillating field with amplitude of 30 Oe was sufficient to destabilize these metastable states; however, a high oscillating field (amplitude > 250 Oe) is required to reduce the remanence to zero.

Boolean and non-boolean nearest neighbor architectures for out-of-plane nanomagnet logic

Abstract: We present the design and simulation of information processing hardware that is comprised of single domain, Co/Pt magnets (i.e., out-of-plane nanomagnet logic - or oNML). We first describe the design and evaluation of oNML hardware that can identify instances of a preprogrammed bit sequence in streaming data. Systolic arrays (that process information using Boolean logic gates) are employed as a system-level architecture which can (i) mitigate less desirable features of the oNML device architecture (nearest neighbor dataflow and longer device switching times when compared to a CMOS transistor), and (ii) exploit unique features of the device architecture (non-volatility and inherently pipelined logic with no overhead). We conclude the paper with a discussion as to how oNML might be employed for non-Boolean information processing. A simple image processing function is used as an initial case study.

A Reconfigurable PLA Architecture for Nanomagnet Logic

Abstract: In order to continue the performance and scaling trends that we have come to expect from Moore’s Law, many emergent computational models, devices, and technologies are actively being studied to either replace or augment CMOS technology. Nanomagnet Logic (NML) is one such alternative. NML operates at room temperature, it has the potential for low power consumption, and it is CMOS compatible. In this aricle, we present an NML programmable logic array (PLA) based on a previously proposed reprogrammable quantum-dot cellular automata PLA design. We also discuss the fabrication and simulation validation of the circuit structures unique to the NML PLA, present area, energy, and delay estimates for the NML PLA, compare the area of NML PLAs to other reprogrammable nanotechnologies, and analyze how architectural-level redundancy will affect performance and defect tolerance in NML PLAs. We will use results from this study to shape a concluding discussion about, which architectures appear to be most suitable for NML.

Magnetic Properties of Enhanced Permeability Dielectrics for Nanomagnetic Logic Circuits

Abstract: Enhanced permeability dielectric (EPD) samples were fabricated in an ultra-high-vacuum magnetron sputtering system, and their magnetic properties were studied by a variable-temperature vibrating sample magnetometer. EPDs were fabricated with layers of CoFe forming uniform particles separated by MgO dielectric as insulator. The optimal sample has peak relative low-field permeability (μr) of 452, saturation magnetization (Ms) of 636 emu/cm3 and magnetization at 100 Oe (M100 Oe) of 398 emu/cm3. Effect of low temperature is discussed, and measurements show that the EPD remains superparamagnetic at 173 K; μr, Ms and M100 Oe values at reduced temperatures are higher than those at room temperature. The sample is ferromagnetic at 100 K.

Direct Measurement of Magnetic Coupling Between Nanomagnets for Nanomagnetic Logic Applications

Abstract: An experimental and computational study of coupling between lithographically fabricated, near-single-domain nanomagnets is presented. Pairs of coupled nanomagnets were fabricated, and their switching properties were characterized by a vibrating sample magnetometer with vector coils. Coupling fields between on-chip nanomagnets compete with (known) magnetic fields that are externally generated. Consequently, nanomagnets flip in the direction of the stronger contribution. Using this method, the volume-averaged coupling field can be directly measured. The experimental data was compared to results from micromagnetic simulations and macrospin models. Correlating the experimental results with simulations reveals the details of the switching process of nanomagnets, and shows the limitations of the macrospin model.

Systolic architectures and applications for nanomagnet logic

Abstract: Most NML research has studied small magnet ensembles for interconnect or isolated gates. We discuss how NML might be used to process information, as well as suitable system architecture-to-device architecture mappings. A case study for pattern matching hardware is presented.

Making non-volatile nanomagnet logic non-volatile

Abstract: Field-coupled nanomagnets can offer significant energy savings at iso-performance versus CMOS equivalents. Magnetic logic could be integrated with CMOS, operate in environments that CMOS cannot, and retain state without power. Clocking requirements lead to inherently pipelined circuits, and high throughput further improves application-level performance. However, bit conflicts -- that will occur in defect free, pipelined ensembles -- can make non-volatile logic volatile. Assuming a field-based clock, we present hardware designs to improve steady state non-volatility, and explain how design enhancements could increase clock energy. We then suggest materials-related design levers that could simultaneously deliver non-volatility and low clock energy.

NanoMagnet logic

Abstract: We present recent results on implementing logic using physically- coupled nanomagnet arrays. The binary state of a bit is represented by the magnetization state of a single-domain nanomagnet element, and logic is accomplished through direct physical interactions between them. We refer to this approach as nanomagnet logic (NML). We have demonstrated that NML satisfies the requirements for digital logic, and offers performance advantages, primarily low power and non-volatility, as a potential post-CMOS technology.

Design of a systolic pattern matcher for Nanomagnet Logic

Abstract: Nanomagnet Logic (NML) is widely considered to be one of the promising for “beyond-CMOS” nanoscale architectures. So far only relatively simple circuits (nanomagnetic logic gates and adders) have been studied experimentally and in simulations. Here we investigate the possibility of building larger-scale computing devices from out-of-plane NML. We designed a systolic pattern matcher circuit that is in principle scalable to arbitrary number of nanomagnets and can match arbitrarily long patterns in an incoming data stream. The design of this systolic architecture for NML makes an important step toward large-scale devices.

Power reduction in nanomagnetic logic clocking through high permeability dielectrics

Abstract: Nanomagnetic logic (NML) has emerged as a novel paradigm to realize non-volatile, nanometer scale, ultra-low energy digital logic [1]. Since there are large energy differences between magnetization states, an external stimulus is required for circuit re-evaluation. In our first experiments we applied an off-chip magnetic field along the hard (i.e., short) axis of a group of nanomagnets. Later, structures that generate fields on-chip were demonstrated [2]. These current-carrying copper wires clad with ferromagnetic material (Supermalloy, Ni 79 Fe 16 Mo 5 ), can provide local magnetic fields for NML circuits. However, the required current densities could be as high as ∼107 A/cm2 [2]. The ratio of flux density to magnetic field strength (μ = B/H) can be increased by surrounding the magnets with a material of high permeability. While we will need to ensure that the binary state of a magnet is not adversely affected, candidate materials do exist. Freescale demonstrated enhanced permeability dielectrics (EPDs) with embedded magnetic nano-particles to increase the field from a word or bit line in field MRAM without increasing current [3]. That EPD particle sizes are below the superparamagnetic limit helps to ensure that a magnet's state is not unduly influenced. With similar considerations, we have proposed a clocking structure where EPD films surround the nanomagnets, as shown in Fig. 1. With this new design, the magnetic flux can be confined within the EPD film area instead of leaking to the air. As such, the field intensity for switching the nanomagnets can be increased, and the required current density and power for clocking can be reduced (potenitially by μ r 2 in the case of power). This work shows our efforts of integrating EPD films with nanomagnets for NML clocking.

Application of Nanomagnetic Logic: Co/Pt based Systolic Pattern Matcher

Abstract: Nanomagnet Logic (NML) is widely considered to be one of the promising for “beyond-CMOS” nanoscale architectures. So far only relatively simple circuits (nanomagnetic logic gates and adders) have been studied experimentally and in simulations. Here we investigate the possibility of building larger-scale computing devices from out-of-plane NML. We designed a systolic pattern matcher circuit that is in principle scalable to arbitrary number of nanomagnets and can match arbitrarily long patterns in an incoming data stream. The design of this systolic architecture for NML makes an important step toward large-scale devices.

Network on metachip architectures

Abstract: The size of systems on a chip is limited by our ability to design and fabricate such systems, staying within the appropriate costs depending on the application. In this paper, we propose a divide-and-conquer approach, Quilt Packaging®, to be utilized for reducing the fabrication costs of large digital systems by partitioning them into a quilted "metachip" that offers integration density and performance merits surpassing the traditional system-on-chip. The physical partitioning and the network-on-a-quilt are closely linked, and should be designed concurrently. For this purpose, we present calculations on the silicon cost of the interconnects and partitioning, discuss the network granularity, and propose a multiprocessor design around a quilted modular network, offering novel techniques to improve the performance and enable true heterogeneous integration. Specifically, the silicon costs of the quilting method are demonstrated to be around 1% of the chip area, while the yield benefits can be in the tens of percents regime. The metachip concept enables the combination of standard high-density memory technologies and wide-bus access with improved performance, typically at least doubling the amount of memory vs. single-chip CMOS. Our modular quilted network enables the integration of non-CMOS chips into the quilt.