H
Hasan Hassan
Researcher at ETH Zurich
Publications - 56
Citations - 3104
Hasan Hassan is an academic researcher from ETH Zurich. The author has contributed to research in topics: Dram & Memory controller. The author has an hindex of 24, co-authored 56 publications receiving 2093 citations. Previous affiliations of Hasan Hassan include Carnegie Mellon University & TOBB University of Economics and Technology.
Papers
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Proceedings ArticleDOI
Ambit: in-memory accelerator for bulk bitwise operations using commodity DRAM technology
Vivek Seshadri,Donghyuk Lee,Thomas Mullins,Hasan Hassan,Amirali Boroumand,Jeremie S. Kim,Michael Kozuch,Onur Mutlu,Phillip B. Gibbons,Todd C. Mowry +9 more
TL;DR: Ambit is proposed, an Accelerator-in-Memory for bulk bitwise operations that largely exploits existing DRAM structure, and hence incurs low cost on top of commodity DRAM designs (1% of DRAM chip area).
Proceedings ArticleDOI
Understanding Latency Variation in Modern DRAM Chips: Experimental Characterization, Analysis, and Optimization
Kevin K. Chang,Abhijith Kashyap,Hasan Hassan,Saugata Ghose,Kevin Hsieh,Donghyuk Lee,Tianshi Li,Gennady Pekhimenko,Samira Khan,Onur Mutlu +9 more
TL;DR: Flexible-LatencY DRAM is proposed, a mechanism that exploits latency variation across DRAM cells within a DRAM chip to improve system performance and exploit the spatial locality of slower cells within DRAM, and access the faster DRAM regions with reduced latencies for the fundamental operations.
Proceedings ArticleDOI
Understanding Reduced-Voltage Operation in Modern DRAM Devices: Experimental Characterization, Analysis, and Mechanisms
Kevin K. Chang,Abdullah Giray Yağlıkçı,Saugata Ghose,Aditya Agrawal,Niladrish Chatterjee,Abhijith Kashyap,Donghyuk Lee,Mike O'Connor,Hasan Hassan,Onur Mutlu +9 more
TL;DR: This paper takes a comprehensive approach to understanding and exploiting the latency and reliability characteristics of modern DRAM when the supply voltage is lowered below the nominal voltage level specified by manufacturers.
Journal ArticleDOI
LazyPIM: An Efficient Cache Coherence Mechanism for Processing-in-Memory
Amirali Boroumand,Saugata Ghose,Minesh Patel,Hasan Hassan,Brandon Lucia,Kevin Hsieh,Malladi Krishna T,Zheng Hongzhong,Onur Mutlu +8 more
TL;DR: It is found that LazyPIM improves average performance across a range of PIM applications by 49.1 percent over the best prior approach, coming within 5.5 percent of an ideal PIM mechanism.
Proceedings ArticleDOI
ChargeCache: Reducing DRAM latency by exploiting row access locality
Hasan Hassan,Gennady Pekhimenko,Nandita Vijaykumar,Vivek Seshadri,Donghyuk Lee,Oguz Ergin,Onur Mutlu +6 more
TL;DR: This work develops a low-cost mechanism, called ChargeCache, that enables faster access to recently- accessed rows in DRAM, with no modifications to DRAM chips, based on the key observation that a recently-accessed row has more charge and thus the following access to the same row can be performed faster.