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Suman Sau

Researcher at Siksha O Anusandhan University

Publications -  36
Citations -  603

Suman Sau is an academic researcher from Siksha O Anusandhan University. The author has contributed to research in topics: Field-programmable gate array & Communications system. The author has an hindex of 6, co-authored 35 publications receiving 472 citations. Previous affiliations of Suman Sau include Information Technology University & University of Calcutta.

Papers
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Journal ArticleDOI

Challenges in QCD matter physics --The scientific programme of the Compressed Baryonic Matter experiment at FAIR

T. O. Ablyazimov, +602 more
TL;DR: The Compressed Baryonic Matter (CBM) experiment at FAIR will play a unique role in the exploration of the QCD phase diagram in the region of high net-baryon densities, because it is designed to run at unprecedented interaction rates.
Journal ArticleDOI

Challenges in QCD matter physics - The Compressed Baryonic Matter experiment at FAIR

T. O. Ablyazimov, +586 more
TL;DR: The Compressed Baryonic Matter (CBM) experiment at FAIR will play a unique role in the exploration of the QCD phase diagram in the region of high net-baryon densities, because it is designed to run at unprecedented interaction rates as discussed by the authors.
Proceedings ArticleDOI

A New High Throughput and Area Efficient SHA-3 Implementation

TL;DR: The presented SHA-3 hash implementations employed architectural optimization approaches based on the concepts of unrolling, pipelining and subpipelining which produced a total of five implementations ofSHA-3 which are denoted as Cases I-V in both FPGA and ASIC.
Proceedings ArticleDOI

IoT Based Secure Smart City Architecture Using Blockchain

TL;DR: An IoT based smart city architecture which adopted the blockchain technology preserving all the cryptographic security issues is proposed and comparison of all security parameters with existing literature shows that the architecture is reasonably efficient in terms of security.
Proceedings ArticleDOI

Design and implementation of real time secured RS232 link for multiple FPGA communication

TL;DR: The design and implementation of a 32-bit RSA algorithms is demonstrated by developing suitable Hardware and Software design on Xilinx Spartan- 3E (XC3S500E-FG320) device and the implementation has been tested successfully for real time serial data communication between multiple FPGA devices using the RS232 serial interface.