https://cyberleninka.org/article/n/1380904.pdf

ASAP7: A 7-nm finFET predictive process design kit

Provided are a semiconductor device, which can facilitate a salicide process and can prevent a gate from being damaged due to misalign, and a method of manufacturing of the semiconductor device. The method includes forming a first insulation layer pattern on a substrate having a gate pattern and a source/drain region formed at both sides of the gate pattern, the first insulation layer pattern having an exposed portion of the source/drain region, forming a silicide layer on the exposed source/drain region, forming a second insulation layer on the entire surface of the substrate to cover the first insulation layer pattern and the silicide layer, and forming a contact hole in the second insulation layer to expose the silicide layer.

Semiconductor devices and methods of manufacturing the same

A semiconductor transistor has a structure including a semiconductor substrate, a source region, a drain region and a channel region in between the source region and the drain region. A metal gate, having a top conductive portion of tungsten is provided above the channel region. A first silicon nitride protective layer over the source region and the drain region and a second silicon nitride protective layer over the gate region are provided. The first silicon nitride protective layer and the second silicon nitride protective layer are configured to allow punch-through of the first silicon nitride protective layer while preventing etching through the second silicon nitride protective layer. Source and drain silicide is protected by avoiding fully etching a gate opening unless either the etching used would not harm the silicide, or the silicide and source and drain contacts are created prior to fully etching an opening to the gate for a gate contact.

Silicide protection during contact metallization and resulting semiconductor structures

An advanced stress memorization technique (SMT) for device performance enhancement is presented. A high-tensile nitride layer is selectively deposited on the n+ poly-Si gate electrode as a stressor with poly amorphoriration implantation in advance. And, this high-tensile nitride capping layer will be removed after the poly and SID activation procedures. The stress modulation effect was found to he enhanced and memorized to affect the channel stress underneath the re-crystallized poly-Si gate electrode after this nitride layer removal. More than 15% current drivability improvement was obtained on NMOS without any cost of PMOS degradation, Combining the high tensile nitride sealing layer deposition after silicide process. it was found to gain additional -10% improvement to NMOS. The device integrity and reliability were verified with no deterioration by this simple and compatible SMT process, which is a promising local strain approach for sub-65nm CMOS application.

- Stress Memorization Technique (SMT) by Selectively Strained-Nitride Capping for

We have proposed and investigated a super steep subthreshold slope transistor by introducing negative capacitance of a ferroelectric HfO2 gate insulator to a vertical tunnel FET for energy efficient computing. The channel structure and gate insulator are systematically designed to maximize the $I_{{\rm{on}}}/ I_{{\rm{off}}}$ ratio. The simulation study reveals that the electric field at the tunnel junction can be effectively enhanced by potential amplification due to the negative capacitance. The enhanced electric field increases the band-to-band tunneling rate and $I_{{\rm{on}}}/ I_{{\rm{off}}}$ ratio, which results in 10× higher energy efficiency than in tunnel FET.

Negative Capacitance for Boosting Tunnel FET performance

A system and method for forming and using a liner is provided. An embodiment comprises forming an opening in an inter-layer dielectric over a substrate and forming the liner along the sidewalls of the opening. A portion of the liner is removed from a bottom of the opening, and a cleaning process may be performed through the liner. By using the liner, damage to the sidewalls of the opening from the cleaning process may be reduced or eliminated. Additionally, the liner may be used to help implantation of ions within the substrate.

Semiconductor device and method for forming the same

A highly scaled, high performance 45 nm CMOS technology utilizing extensive immersion lithography to achieve the industry's highest scaling factor with ELK (k=2.55) BEOL is presented. A record gate density 2.4X higher than that of 65 nm is achieved. Refined strained-CMOS demonstrated 1200/750 μA/μm Idsat at 100 nA/μm Ioff, Vdd=1 V, which has the best Ion-Lg performance reported for bulk CMOS device. The proposed 45 nm technology is not only manufacturing friendly but also has well-controlled leakage and mismatch evidenced by a functional 32 Mb 0.242 μm2 SRAM.

A highly scaled, high performance 45 nm bulk logic CMOS technology with 0.242 μm 2 SRAM cell

This study investigates the formation of Ni silicides on Si 1-y C y (0 ≤ y ≤ 0.02) epilayers grown on Si(001). The presence of C atoms retards the growth kinetics of NiSi and significantly enhances the thermal stability of NiSi thin films. In particular, an abnormal redistribution of C atoms in the NiSi thin films was observed during Ni silicidation. The NiSi layer was split into two sublayers by an obvious pileup of C atoms. This study proposes a mechanism to elucidate this phenomenon in terms of the C solubility. C atoms accumulated at the NiSi/S 1-y C y interfaces and NiSi grain boundaries may act as diffusion barriers, effectively hindering the grain growth and agglomeration of NiSi and extending the process window of low resistivity NiSi silicides.

C Redistribution during Ni Silicide Formation on Si1 − y C y Epitaxial Layers

We demonstrate, for the first time, an integration-friendly selective PMOSFET fully silicided (FUSI) gate process. In this process, a millisecond-anneal (MSA) technique is utilized for the nickel silicide phase transformation. A highly tensile FUSI gate electrode is created and hence exerts compressive stress in the underlying channel. The highly flexible integration scheme successfully, and exclusively, implements uniform P+ FUSI gates for PMOSFETs while preserving a FUSI-free N+ poly-Si gate for NMOSFETs with the feature size down to 30 nm. A 20% improvement in FUSI- gated PMOSFET Ion- Ioff is measured, which can be attributed to the enhanced hole mobility and the elimination of P+ poly-gate depletion.

https://ir.nctu.edu.tw:443/bitstream/11536/8432/1/000259573400009.pdf

Ming-Ta Lei

Papers

Semiconductor device and method for forming the same

A highly scaled, high performance 45 nm bulk logic CMOS technology with 0.242 μm 2 SRAM cell

C Redistribution during Ni Silicide Formation on Si1 − y C y Epitaxial Layers

A Millisecond-Anneal-Assisted Selective Fully Silicided (FUSI) Gate Process