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Chun-Kuang Chen
Researcher at TSMC
Publications - 75
Citations - 961
Chun-Kuang Chen is an academic researcher from TSMC. The author has contributed to research in topics: CMOS & Immersion lithography. The author has an hindex of 14, co-authored 72 publications receiving 869 citations.
Papers
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Proceedings ArticleDOI
A 16nm FinFET CMOS technology for mobile SoC and computing applications
Shien-Yang Wu,Lin Chih-Yung,M.C. Chiang,Jhon-Jhy Liaw,Joy Cheng,S.H. Yang,Liang Min-Chang,T. Miyashita,C.H. Tsai,B. C. Hsu,H. Y. Chen,T. Yamamoto,S.Y. Chang,Vincent S. Chang,C.H. Chang,J.H. Chen,Hou-Yu Chen,Kai-Yuan Ting,Y.K. Wu,K.H. Pan,R.F. Tsui,C.H. Yao,P. R. Chang,H. M. Lien,Tze-Liang Lee,H. M. Lee,W. Chang,T. Chang,R. Chen,M. Yeh,Chun-Kuang Chen,Yuan-Hung Chiu,Y. H. Chen,H. C. Huang,Y. C. Lu,Chang Chih-Yang,Ming-Huan Tsai,C. C. Liu,Kuei-Shun Chen,C. C. Kuo,H. T. Lin,S. M. Jang,Y. Ku +42 more
TL;DR: This is the smallest fully functional 128Mb HD FinFET SRAM (with single fin) test-chip demonstrated with low Vccmin for 16nm node and provides 2X logic density and 2X speed gain over 28nm HK/MG planar technology.
Proceedings ArticleDOI
A 7nm CMOS platform technology featuring 4 th generation FinFET transistors with a 0.027um 2 high density 6-T SRAM cell for mobile SoC applications
Shien-Yang Wu,Lin Chih-Yung,M.C. Chiang,Jhon-Jhy Liaw,Joy Cheng,S.H. Yang,C.H. Tsai,P N Chen,T. Miyashita,C.H. Chang,Vincent S. Chang,K.H. Pan,J.H. Chen,Y S Mor,K T Lai,C S Liang,Hou-Yu Chen,S.Y. Chang,Chia-Pin Lin,C. H. Hsieh,R.F. Tsui,C.H. Yao,Chun-Kuang Chen,R. Chen,C. H. Lee,Hon-Jarn Lin,Chang Chih-Yang,Kuang-Hsin Chen,Ming-Huan Tsai,Kuei-Shun Chen,Y. Ku,S. M. Jang +31 more
TL;DR: In this paper, the authors presented a leading edge 7nm CMOS platform technology for mobile SoC applications, which provides >3.3X routed gate density and 35%∼40% speed gain or >65% power reduction over 16nm FinFET technology.
Proceedings ArticleDOI
5nm CMOS Production Technology Platform featuring full-fledged EUV, and High Mobility Channel FinFETs with densest 0.021µm 2 SRAM cells for Mobile SoC and High Performance Computing Applications
Geoffrey Yeap,X. Chen,B. R. Yang,C. P. Lin,F. C. Yang,Y. K. Leung,Derek Lin,C. P. Chen,K. F. Yu,D. H. Chen,Chun-Yen Chang,S.S. Lin,Huan-Neng Chen,P. Hung,Chuan-Ping Hou,Cheng Yun-Wei,Jonathan Chang,L. Yuan,Chung-Kai Lin,Chun-Kuang Chen,Yee-Chia Yeo,Ming-Huan Tsai,Yung-Shun Chen,Hsien-Chin Lin,C. O. Chui,Kevin Huang,W. Chang,Hon-Jarn Lin,Kuang-Hsin Chen,R. Chen,S. H. Sun,Q. Fu,H. T. Yang,H. L. Shang,H. T. Chiang,C. C. Yeh,Tze-Liang Lee,C. H. Wang,S. L. Shue,C. W. Wu,Ryan Lu,Wei-Heng Lin,Jau-Yi Wu,F. L. Lai,Po-Kang Wang,Yung-Hsien Wu,B. Z. Tien,Y. C. Huang,L. C. Lu,Jun He,Y. Ku,Jing-Cheng Lin,M. Cao,T. S. Chang,S. M. Jang,H. C. Lin,Yung-Chow Peng,Jyh-Cherng Sheu,Ming-Fang Wang +58 more
TL;DR: The 5nm platform technology successfully passed qualification with consistently high yielding 256Mb HD/HC SRAM, and large logic test chip consisting of CPU/GPU/SoC blocks, on schedule for high volume production in 1H 2020.
Proceedings ArticleDOI
An enhanced 16nm CMOS technology featuring 2 nd generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications
Shien-Yang Wu,Lin Chih-Yung,M.C. Chiang,Jhon-Jhy Liaw,Joy Cheng,S.H. Yang,S.Z. Chang,Liang Min-Chang,T. Miyashita,C.H. Tsai,C.H. Chang,Vincent S. Chang,Y.K. Wu,J.H. Chen,Hou-Yu Chen,S.Y. Chang,K.H. Pan,R.F. Tsui,C.H. Yao,Kai-Yuan Ting,T. Yamamoto,H.T. Huang,Tze-Liang Lee,C. H. Lee,W. Chang,H. M. Lee,Chun-Kuang Chen,T. Chang,R. Chen,Yuan-Hung Chiu,Ming-Huan Tsai,S. M. Jang,Kuei-Shun Chen,Y. Ku +33 more
TL;DR: In this paper, an enhanced 16nm CMOS technology featuring the second generation FinFET transistors and advanced Cu/low-k interconnect is presented to provide additional 15% speed boost or 30% power reduction.
Proceedings Article
A highly manufacturable 28nm CMOS low power platform technology with fully functional 64Mb SRAM using dual/tripe gate oxide process
Shien-Yang Wu,Jhon-Jhy Liaw,Lin Chih-Yung,M.C. Chiang,C.K. Yang,Joy Cheng,Ming-Huan Tsai,M.Y. Liu,P.H. Wu,C.H. Chang,L.C. Hu,C.I. Lin,Hou-Yu Chen,S.Y. Chang,S.H. Wang,P.Y. Tong,Y.L. Hsieh,K.H. Pan,C. H. Hsieh,C.H. Chen,C.H. Yao,Chun-Kuang Chen,T.L. Lee,Chang Chih-Yang,Hon-Jarn Lin,Shih-Chang Chen,J.H. Shieh,S.M. Jang,Kuei-Shun Chen,Y. Ku,Yee Chaung See,W.J. Lo +31 more
TL;DR: In this article, the authors presented a 64 Mb SRAM test-chip with the smallest cell using dual/triple gate oxide process flow in 28 nm node, which achieved competitive mismatch (AVt of 2.86 mV) and 1/f noise characteristics.