Ming Zhang

TL;DR: In this article, the parasitic resistance of different source/drain metals for top-gated graphene field effect transistors was extracted by fitting the measured ID-VG data with a resistance model and was found to be a significant part of the total resistance of graphene field-effect transistors.

TL;DR: It is found that after graphene film transfer, an annealing process at 400 °C under N 2 ambient will shift Dirac point toward zero gate voltage, which is the highest value among CVD graphene FETs published to date.

TL;DR: In this article, the authors report a scalable technique to fabricate graphene transistors with self-aligned buried gates process, which has excellent field effect mobility of 6,100cm2/V·s and 24,000 cm2/v·s before and after subtraction of contact resistance.

TL;DR: In this paper, a top-gate and buried-gate structure with self-aligned buried gates has been proposed for high-performance graphene transistors with field effect mobility of over 6,000 cm2/V

TL;DR: In this article, a scalable technique to fabricate high performance graphene transistors with self-aligned buried gates process is presented, which shows less fringing capacitance and more reliable contacts.