Minho Kwon

TL;DR: An offset canceling circuit stores charge corresponding to a voltage difference between a reset voltage received from a unit pixel and a reference voltage, thereby canceling an offset of the unit pixel.

TL;DR: In this article, the analog-to-digital converter includes a modulation unit and a digital signal generation unit, and the modulation unit is disposed corresponding to at least one column line, and sequentially performs delta-sigma modulation on an analog input signal and at least 1 residue voltage to generate digital bit stream signals.

TL;DR: This brief proposes a multiplexing scheme to realize an I/Q-channel time-interleaved (TI) bandpass sigma-delta modulator that shares operational transconductance amplifiers to minimize power consumption and silicon area for a low-intermediate-frequency (IF) wireless receiver.

TL;DR: A time-interleaved recursive loop BPDSM architecture that consists of five-stage TI blocks for a code-division multiple-access (CDMA) receiver is proposed that provides reduction in the clock frequency requirement by a factor of 5 and relaxes the settling time requirement to one-fourth of the conventional approach.

TL;DR: Simulation results show that the proposed ADC BIST scheme can detect not only catastrophic faults but also some parametric faults and the total gate count of the proposed BIST circuit is about 150.