Developing next-generation cellular technology (5G) in the mm-wave bands will require low-cost phased-array transceivers [1]. Even with the benefit of beamforming, due to space constraints in the mobile form-factor, increasing TX output power while maintaining acceptable PA PAE, LNA NF, and overall transceiver power consumption is important to maximizing link budget allowable path loss and minimizing handset case temperature. Further, the phased-array transceiver will need to be able to support dual-polarization communication. An IF interface to the analog baseband is desired for low power consumption in the handset or user equipment (UE) active antenna and to enable use of arrays of transceivers for customer premises equipment (CPE) or basestation (BS) antenna arrays with a low-loss IF power-combining/splitting network implemented on an antenna backplane carrying multiple tiled antenna modules.

A 28GHz Bulk-CMOS dual-polarization phased-array transceiver with 24 channels for 5G user and basestation equipment

This paper describes a 28-GHz CMOS direct conversion transceiver with packaged $2 \times 4$ patch antenna array for 5G communication. Beamforming antenna and reconfigurable transceiver architecture are used for high effective isotropic radiated power (EIRP). For low error vector magnitude (EVM), switchless matching transmitter (Tx)/receiver (Rx) to antenna and 28-GHz injection-locked local oscillator (LO) generator are employed. Test chip was fabricated in 28-nm RF CMOS process. Measurement results show Tx EIRPsat of 31.5 dBm ( $P_{\mathrm {sat}}$ of 10.5 dBm in one power amplifier (PA)), EIRPmax 24 dBm ( $P_{\mathrm {max}}$ of 2 dBm with backoff of 7.5 dB in one PA), Rx noise figure of 6.7 dB, and integrated LO phase noise of −38.7 dBc (0.67°). After IQ mismatch calibration, Tx LO leakage and image power are less than −35 dBc. Rx and Tx EVM show 2.2% (−33 dB) at medium RF power (Rx $P_{\mathrm {in}}$ of −60 dBm and Tx EIRP of 0 dBm) with well-fit beam control capability.

A 28-GHz CMOS Direct Conversion Transceiver With Packaged $2 \times 4$ Antenna Array for 5G Cellular System

This paper presents a 28-GHz CMOS four-element phased-array transceiver chip for the fifth-generation mobile network (5G) new radio (NR). The proposed transceiver is based on the local-oscillator (LO) phase-shifting architecture, and it achieves quasi-continuous phase tuning with less than 0.2-dB radio frequency (RF) gain variation and 0.3°C phase error. Accurate beam control with suppressed sidelobe level during beam steering could be supported by this work. At 28 GHz, a single-element transmitter-mode output ${{\mathrm {P}}_{\mathrm {1\,dB}}}$ of 15.7 dBm and a receiver-mode noise figure (NF) of 4.1 dB are achieved. The eight-element transceiver modules developed in this work are capable of scanning the beam from −50° to +50° with less than −9-dB sidelobe level. A saturated equivalent isotropic radiated power (EIRP) of 39.8 dBm is achieved at 0° scan. In a 5-m over-the-air measurement, the proposed module demonstrates the first 512 quadrature amplitude modulation (QAM) constellation in the 28-GHz band. A data stream of 6.4 Gb/s in 256-QAM could be supported within a beam angle of ±50°. The achieved maximum data rate is 15 Gb/s in 64-QAM. The proposed transceiver chip consumes 1.2 W/chip in transmitter mode and 0.59 W/chip in receiver mode.

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A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio

A wideband amplitude to phase (AM–PM) compensated class-AB power amplifier (PA) suitable for highly integrated fifth-generation phased arrays is designed in 0.9-V 28-nm CMOS without RF ultra-thick top metal. Design techniques to realize broadband impedance transformation, power division/combining, and phase distortion linearization are discussed. Further, second-order effects due to practical layout constrains imposed by deep-scaled technologies are addressed and simple design solutions are proposed. The designed PA shows a measured $S_{21} -3$ dB bandwidth (BW) from 29 to 57 GHz (65%) with $|\text {AM}-\text {PM}| up to $P_{1~\text {dB}}$ . The measured $P_{\mathrm{ sat}}$ is 15.1 dBm over >56% $\text {BW}_{-1~\text {dB}}$ , with a peak power added efficiency of 24.2%. When a signal with wide modulation BW is applied, the realized PA enables up to 10.1-, 8.9-, and 5.9-dBm average $P_{\mathrm{ OUT}}$ while amplifying a 1.5-, 3-, and 6-Gb/s 64-quadratic-amplitude modulation, respectively, at 34 GHz. The in-band and out-of-band linearity measured in error vector magnitude and adjacent channel power ratio are always better than −25 dB and −30 dBc, respectively, without any digital pre-distortion.

A Wideband Class-AB Power Amplifier With 29–57-GHz AM–PM Compensation in 0.9-V 28-nm Bulk CMOS

Recently, we demonstrated the first CMOS nonmagnetic nonreciprocal passive circulator based on N-path filters that uses time variance to break reciprocity. Here, the analysis of performance metrics, such as loss, isolation, linearity, and tuning range, is presented in terms of the design parameters. The analysis is verified by the measured performance of a 65-nm CMOS circulator prototype that exhibits 1.7 dB of loss in the transmitter-antenna (TX-ANT) and antenna-receiver (ANT-RX) paths, and has high isolation [TX–RX, up to 50 dB through tuning and 20-dB bandwidth (BW) of 32 MHz] and a tuning range of 610–850 MHz. Through an architectural feature specifically designed to enhance TX linearity, the circulator achieves an in-band TX-ANT input-referred third-order intercept point (IIP3) of +27.5 dBm, nearly two orders of magnitude higher than the ANT-RX IIP3 of +8.7 dBm. The circulator is also integrated with a self-interference-canceling full-duplex (FD) RX featuring an analog baseband (BB) SI canceller. The FD RX achieves 42-dB on-chip SI suppression across the circulator and analog BB domains over a 12-MHz signal BW. In conjunction with digital SI and its input-referred third-order intermodulation (IM3) cancellation, the FD RX demonstrates 85-dB overall SI suppression, enabling an FD link budget of −7-dBm TX average output power and −92-dBm noise floor.

A CMOS Passive LPTV Nonmagnetic Circulator and Its Application in a Full-Duplex Receiver

This letter presents a CMOS wideband variable gain LNA for 28-GHz 5G integrated phased-array transceivers preserving high third-order intercept point (OIP3) at all gain settings. The prototype LNA has three stages providing digitally controlled gain optimized for higher IIP3 at lower gain. The stages are coupled together using double-tuned transformers for maximum group delay flatness. Fabricated in a 40-nm CMOS process, it achieves 18–26 dB gain at 1-dB gain step with 12–14.5 dBm OIP3 and 3.3–4.3 dB noise figure, while consuming 21.5–31.4 mW across 26–33 GHz frequency range. The root-mean-square error of the gain steps is less than 0.38 dB.

A Wideband Variable Gain LNA With High OIP3 for 5G Using 40-nm Bulk CMOS

To meet rising demand, broadband-cellular-data providers are racing to deploy fifth generation (5G) mm-wave technology, e.g., rollout of some 28GHz-band services is intended in 2017 in the USA with ∼5/1Gb/s downlink/uplink targets. Even with 64-QAM signaling, this translates to an RF bandwidth (RFBW) as large as ∼800MHz. With ∼100m cells and a dense network of 5G access points (APs), potential manufacturing volumes make low-cost CMOS technology attractive for both user equipment (UE) and AP devices. However, the poor P out and linearity of CMOS power amplifiers (PAs) are a bottleneck, as ∼10dB back-off is typical for meeting error-vector-magnitude (EVM) specifications. This limits communication range and PA power added efficiency (PAE), with wider RFBWs accentuating these issues further. On the other hand, sufficient element counts in the envisaged 5G phased-array modules can overcome path loss despite low P out per PA, e.g., by combining RFICs in an AP. CMOS PAs with wideband linearity/PAE can therefore enable economical UE/AP devices to deliver 5G data-rates.

2.7 A wideband 28GHz power amplifier supporting 8×100MHz carrier aggregation for 5G in 40nm CMOS

A tunable integrated electrical balanced duplexer (EBD) is presented as a compact alternative to multiple bulky surface acoustic wave (SAW) and bulk acoustic wave (BAW) duplexers in third-generation (3G)/fourth-generation (4G) cellular transceivers. A balancing network creates a replica of the transmitter (TX) signal for cancellation at the input of a single-ended low-noise amplifier (LNA) to isolate the receive path from the TX. The proposed passive EBD is based on a cross-connected transformer topology without the need of any extra baluns at the antenna side. The balancing network enables a single-ended LNA with reliable high TX power operation up to 22 dBm by alleviating the common-mode coupling. The duplexer achieves around 50-dB transmitter–receiver (TX-RX) isolation within a 1.6–2.2-GHz range. The cascaded noise figure (NF) of the duplexer and LNA is 6.5 dB, and TX insertion loss (TXIL) of the duplexer is about 3.2 dB. The duplexer and LNA are implemented in a ${\hbox{0.18-}}\mu{\hbox{m}}$ CMOS process and occupy an active area of ${\hbox{0.35 mm}}^{2}$ .

Low-Loss Integrated Passive CMOS Electrical Balance Duplexers With Single-Ended LNA

This paper reports a transmit–receive (Tx–Rx) front-end (FE) in bulk CMOS targeting fifth-generation (5G) mobile user equipment (UE)-phased arrays. Block-level specifications are first reviewed based on link budget and UE array beam steering considerations, and compared against measured standalone power/low-noise amplifier and phase shifter test circuit performances. Then, the codesign of the Tx–Rx switch and antenna impedance matching is investigated for the important case of wideband dual-resonance networks, leading to a proposed topology that is experimentally verified using silicon passive test structures. A fully integrated FE prototype is fabricated in 1.1-V 1P6M 40-nm bulk CMOS and characterized in detail across digital gain and phase settings. Measurements show Tx-mode $P_{\mathrm {1\,dB}}$ /PAE1 dB ≥ 14.6 dBm/21.9% across 27–30 GHz, and peak $P_{\mathrm{ out}}$ /PAE = 6.5dBm/8.8% at 27 GHz for an $8\,\,\times100$ -MHz carrier-aggregated 64-QAM OFDM signal. In Rx-mode, a noise figure of 5.5–6 dB and an input-referred third-order intercept point of −8.5 to −6 dBm are achieved across 27–33 GHz. Normalized to area/power consumption, the achieved performance is the state of the art relative to the most recent CMOS/SiGe FEs.

A Wideband 28-GHz Transmit–Receive Front-End for 5G Handset Phased Arrays in 40-nm CMOS

A highly sensitive CMOS-based sensing system is proposed for permittivity detection and mixture characterization of organic chemicals at microwave frequencies The system determines permittivity by measuring the frequency difference between two voltage-controlled oscillators (VCOs); a sensor oscillator with an operating frequency that shifts with the change in tank capacitance due to exposure to the material under test (MUT) and a reference oscillator insensitive to the MUT This relative measurement approach improves sensor accuracy by tracking frequency drifts due to environmental variations Embedding the sensor and reference VCOs in a fractional- N phase-locked loop (PLL) frequency synthesizer enables material characterization at a precise frequency and provides an efficient material-induced frequency shift read-out mechanism with a low-complexity bang-bang control loop that adjusts a fractional frequency divider The majority of the PLL-based sensor system, except for an external fractional frequency divider, is implemented with a 90-nm CMOS prototype that consumes 22 mW when characterizing material near 10 GHz Material-induced frequency shifts are detected at an accuracy level of 15 ppmrms and binary mixture characterization of organic chemicals yield maximum errors in permittivity of 15%

Mohamed Elkholy

Papers

A Wideband Variable Gain LNA With High OIP3 for 5G Using 40-nm Bulk CMOS

2.7 A wideband 28GHz power amplifier supporting 8×100MHz carrier aggregation for 5G in 40nm CMOS

Low-Loss Integrated Passive CMOS Electrical Balance Duplexers With Single-Ended LNA

A Wideband 28-GHz Transmit–Receive Front-End for 5G Handset Phased Arrays in 40-nm CMOS

A CMOS Fractional- $N$ PLL-Based Microwave Chemical Sensor With 1.5% Permittivity Accuracy