This paper presents a scalable 28-GHz phased-array architecture suitable for fifth-generation (5G) communication links based on four-channel ( $2\times 2$ ) transmit/receive (TRX) quad-core chips in SiGe BiCMOS with flip-chip packaging. Each channel of the quad-core beamformer chip has 4.6-dB noise figure (NF) in the receive (RX) mode and 10.5-dBm output 1-dB compression point (OP1dB) in the transmit (TX) mode with 6-bit phase control and 14-dB gain control. The phase change with gain control is only ±3°, allowing orthogonality between the variable gain amplifier and the phase shifter. The chip has high RX linearity (IP1dB = −22 dBm/channel) and consumes 130 mW in the RX mode and 200 mW in the TX mode at P1dB per channel. Advantages of the scalable all-RF beamforming architecture and circuit design techniques are discussed in detail. 4- and 32-element phased-arrays are demonstrated with detailed data link measurements using a single or eight of the four-channel TRX core chips on a low-cost printed circuit board with microstrip antennas. The 32-element array achieves an effective isotropic radiated power (EIRP) of 43 dBm at P1dB, a 45-dBm saturated EIRP, and a record-level system NF of 5.2 dB when the beamformer loss and transceiver NF are taken into account and can scan to ±50° in azimuth and ±25° in elevation with < −12-dB sidelobes and without any phase or amplitude calibration. A wireless link is demonstrated using two 32-element phased-arrays with a state-of-the-art data rate of 1.0–1.6 Gb/s in a single beam using 16-QAM waveforms over all scan angles at a link distance of 300 m.

A Low-Cost Scalable 32-Element 28-GHz Phased Array Transceiver for 5G Communication Links Based on a $2\times 2$ Beamformer Flip-Chip Unit Cell

Developing next-generation cellular technology (5G) in the mm-wave bands will require low-cost phased-array transceivers [1]. Even with the benefit of beamforming, due to space constraints in the mobile form-factor, increasing TX output power while maintaining acceptable PA PAE, LNA NF, and overall transceiver power consumption is important to maximizing link budget allowable path loss and minimizing handset case temperature. Further, the phased-array transceiver will need to be able to support dual-polarization communication. An IF interface to the analog baseband is desired for low power consumption in the handset or user equipment (UE) active antenna and to enable use of arrays of transceivers for customer premises equipment (CPE) or basestation (BS) antenna arrays with a low-loss IF power-combining/splitting network implemented on an antenna backplane carrying multiple tiled antenna modules.

A 28GHz Bulk-CMOS dual-polarization phased-array transceiver with 24 channels for 5G user and basestation equipment

Here, we propose a fully metallic implementation of a Luneburg lens operating at Ka-band with potential use for 5G communications. The lens is implemented with a parallel plate that is loaded with glide-symmetric holes. These holes are employed to produce the required equivalent refractive index profile of a Lune-burg lens. Glide symmetry and inner metallic pins are employed to increase the equivalent refractive index. The lens is fed with rectangular waveguides designed to match the height of the parallel plate, and it is ended with a flare to minimize the reflections.

Glide-Symmetric Fully Metallic Luneburg Lens for 5G Communications at K a -Band

Research and development on the next generation wireless systems, namely 5G, has experienced explosive growth in recent years. In the physical layer, the massive multiple-input-multiple-output (MIMO) technique and the use of high GHz frequency bands are two promising trends for adoption. Millimeter-wave (mmWave) bands, such as 28, 38, 64, and 71 GHz, which were previously considered not suitable for commercial cellular networks, will play an important role in 5G. Currently, most 5G research deals with the algorithms and implementations of modulation and coding schemes, new spatial signal processing technologies, new spectrum opportunities, channel modeling, 5G proof of concept systems, and other system-level enabling technologies. In this paper, we first investigate the contemporary wireless user equipment (UE) hardware design, and unveil the critical 5G UE hardware design constraints on circuits and systems. On top of the said investigation and design tradeoff analysis, a new, highly reconfigurable system architecture for 5G cellular user equipment, namely distributed phased arrays based MIMO (DPA-MIMO) is proposed. Finally, the link budget calculation and data throughput numerical results are presented for the evaluation of the proposed architecture.

5G Cellular User Equipment: From Theory to Practical Hardware Design

This paper describes a 28-GHz CMOS direct conversion transceiver with packaged $2 \times 4$ patch antenna array for 5G communication. Beamforming antenna and reconfigurable transceiver architecture are used for high effective isotropic radiated power (EIRP). For low error vector magnitude (EVM), switchless matching transmitter (Tx)/receiver (Rx) to antenna and 28-GHz injection-locked local oscillator (LO) generator are employed. Test chip was fabricated in 28-nm RF CMOS process. Measurement results show Tx EIRPsat of 31.5 dBm ( $P_{\mathrm {sat}}$ of 10.5 dBm in one power amplifier (PA)), EIRPmax 24 dBm ( $P_{\mathrm {max}}$ of 2 dBm with backoff of 7.5 dB in one PA), Rx noise figure of 6.7 dB, and integrated LO phase noise of −38.7 dBc (0.67°). After IQ mismatch calibration, Tx LO leakage and image power are less than −35 dBc. Rx and Tx EVM show 2.2% (−33 dB) at medium RF power (Rx $P_{\mathrm {in}}$ of −60 dBm and Tx EIRP of 0 dBm) with well-fit beam control capability.

A 28-GHz CMOS Direct Conversion Transceiver With Packaged $2 \times 4$ Antenna Array for 5G Cellular System

This paper presents the first linear bulk CMOS power amplifier (PA) targeting low-power fifth-generation (5G) mobile user equipment integrated phased array transceivers. The output stage of the PA is first optimized for power-added efficiency (PAE) at a desired error vector magnitude (EVM) and range given a challenging 5G uplink use case scenario. Then, inductive source degeneration in the optimized output stage is shown to enable its embedding into a two-stage transformer-coupled PA; by broadening interstage impedance matching bandwidth and helping to reduce distortion. Designed and fabricated in 1P7M 28 nm bulk CMOS and using a 1 V supply, the PA achieves +4.2 dBm/9% measured $P_{\text {out}}$ /PAE at −25 dBc EVM for a 250 MHz-wide 64-quadrature amplitude modulation orthogonal frequency division multiplexing signal with 9.6 dB peak-to-average power ratio. The PA also achieves 35.5%/10% PAE for continuous wave signals at saturation/9.6 dB back-off from saturation. To the best of the authors’ knowledge, these are the highest measured PAE values among published ${K}$ - and Ka -band CMOS PAs.

A Highly Efficient and Linear Power Amplifier for 28-GHz 5G Phased Array Radios in 28-nm CMOS

This letter presents a CMOS wideband variable gain LNA for 28-GHz 5G integrated phased-array transceivers preserving high third-order intercept point (OIP3) at all gain settings. The prototype LNA has three stages providing digitally controlled gain optimized for higher IIP3 at lower gain. The stages are coupled together using double-tuned transformers for maximum group delay flatness. Fabricated in a 40-nm CMOS process, it achieves 18–26 dB gain at 1-dB gain step with 12–14.5 dBm OIP3 and 3.3–4.3 dB noise figure, while consuming 21.5–31.4 mW across 26–33 GHz frequency range. The root-mean-square error of the gain steps is less than 0.38 dB.

A Wideband Variable Gain LNA With High OIP3 for 5G Using 40-nm Bulk CMOS

To meet rising demand, broadband-cellular-data providers are racing to deploy fifth generation (5G) mm-wave technology, e.g., rollout of some 28GHz-band services is intended in 2017 in the USA with ∼5/1Gb/s downlink/uplink targets. Even with 64-QAM signaling, this translates to an RF bandwidth (RFBW) as large as ∼800MHz. With ∼100m cells and a dense network of 5G access points (APs), potential manufacturing volumes make low-cost CMOS technology attractive for both user equipment (UE) and AP devices. However, the poor P out and linearity of CMOS power amplifiers (PAs) are a bottleneck, as ∼10dB back-off is typical for meeting error-vector-magnitude (EVM) specifications. This limits communication range and PA power added efficiency (PAE), with wider RFBWs accentuating these issues further. On the other hand, sufficient element counts in the envisaged 5G phased-array modules can overcome path loss despite low P out per PA, e.g., by combining RFICs in an AP. CMOS PAs with wideband linearity/PAE can therefore enable economical UE/AP devices to deliver 5G data-rates.

2.7 A wideband 28GHz power amplifier supporting 8×100MHz carrier aggregation for 5G in 40nm CMOS

Rapidly growing demand for broadband-cellular-data traffic is driving fifth-generation (5G) wireless standardization towards the deployment of gigabit-per-second mm-Wave technology by 2020. Paving the road to 5G, 200m coverage in non-line-of-sight (NLOS) urban cells was demonstrated using practical antenna arrays at 28GHz [1], and the FCC recently issued a notice of inquiry into the provision of mobile services above 24GHz. Battery life and thermal limitations make power efficiency critical in the envisioned user-equipment (UE) phased-array transceivers, particularly for power amplifiers (PAs), which operate at 8-to-10dB power back-off (PBO) to transmit broadband, high-peak-to-average power-ratio (PAPR) signals with high fidelity. Higher yields and lower costs for integrated phased arrays make CMOS the preferred choice over other more-power-efficient technologies, e.g. GaAs. Furthermore, calibrating an integrated array of PAs, e.g. by using digital pre-distortion, is prohibitively complex for high-volume manufacturing. Thus, maximizing PAE of inherently linear CMOS PA circuits at PBO is a major challenge for future 5G UE radios.

20.6 A 28GHz efficient linear power amplifier for 5G phased arrays in 28nm bulk CMOS

This paper reports a transmit–receive (Tx–Rx) front-end (FE) in bulk CMOS targeting fifth-generation (5G) mobile user equipment (UE)-phased arrays. Block-level specifications are first reviewed based on link budget and UE array beam steering considerations, and compared against measured standalone power/low-noise amplifier and phase shifter test circuit performances. Then, the codesign of the Tx–Rx switch and antenna impedance matching is investigated for the important case of wideband dual-resonance networks, leading to a proposed topology that is experimentally verified using silicon passive test structures. A fully integrated FE prototype is fabricated in 1.1-V 1P6M 40-nm bulk CMOS and characterized in detail across digital gain and phase settings. Measurements show Tx-mode $P_{\mathrm {1\,dB}}$ /PAE1 dB ≥ 14.6 dBm/21.9% across 27–30 GHz, and peak $P_{\mathrm{ out}}$ /PAE = 6.5dBm/8.8% at 27 GHz for an $8\,\,\times100$ -MHz carrier-aggregated 64-QAM OFDM signal. In Rx-mode, a noise figure of 5.5–6 dB and an input-referred third-order intercept point of −8.5 to −6 dBm are achieved across 27–33 GHz. Normalized to area/power consumption, the achieved performance is the state of the art relative to the most recent CMOS/SiGe FEs.

Sherif Shakib

Papers

A Highly Efficient and Linear Power Amplifier for 28-GHz 5G Phased Array Radios in 28-nm CMOS

A Wideband Variable Gain LNA With High OIP3 for 5G Using 40-nm Bulk CMOS

2.7 A wideband 28GHz power amplifier supporting 8×100MHz carrier aggregation for 5G in 40nm CMOS

20.6 A 28GHz efficient linear power amplifier for 5G phased arrays in 28nm bulk CMOS

A Wideband 28-GHz Transmit–Receive Front-End for 5G Handset Phased Arrays in 40-nm CMOS