Showing papers by "Mohamed I. Elmasry published in 2010"

Discrete cooperative particle swarm optimization for FPGA placement

Abstract: Particle swarm optimization (PSO) is a stochastic optimization technique that has been inspired by the movement of birds. On the other hand, the placement problem in field programmable gate arrays (FPGAs) is crucial to achieve the best performance. Simulated annealing algorithms have been widely used to solve the FPGA placement problem. In this paper, a discrete PSO (DPSO) version is applied to the FPGA placement problem to find the optimum logic blocks and IO pins locations in order to minimize the total wire-length. Moreover, a co-operative version of the DPSO (DCPSO) is also proposed for the FPGA placement problem. The problem is entirely solved in the discrete search space and the proposed implementation is applied to several well-known FPGA benchmarks with different dimensionalities. The results are compared to those obtained by the academic versatile place and route (VPR) placement tool, which is based on simulated annealing. Results show that both the DPSO and DCPSO outperform the VPR tool for small and medium-sized problems, with DCPSO having a slight edge over the DPSO technique. For higher-dimensionality problems, the algorithms proposed provide very close results to those achieved by VPR.

A Design-Oriented Soft Error Rate Variation Model Accounting for Both Die-to-Die and Within-Die Variations in Submicrometer CMOS SRAM Cells

Abstract: Submicrometer static random access memory cells are more susceptible to particle strike soft errors and increased statistical process variations, in advanced nanometer CMOS technologies. In this paper, analytical models for the critical charge variations accounting for both die-to-die and within-die variations are proposed. The derived models are verified and compared to Monte Carlo simulations by using industrial 65-nm CMOS technology. This paper provides new design insights such as the impact of the coupling capacitor, one of the most common soft error mitigation techniques, on the critical charge variability, especially, at lower supply voltages. It demonstrates that two extreme values of this coupling capacitor exist. The first value results in maximum relative variations and the other results in minimum relative variations. Therefore, the circuit designers can utilize these results to design the coupling capacitor to limit the variations under power and performance constraints in early design cycles. The derived analytical models account for the impact of the supply voltage and different particle strike conditions. These results are particularly important for soft error tolerant and variation tolerant designs in submicrometer technologies, especially, for low power operations.

A Power-Efficient Multipin ILP-Based Routing Technique

Abstract: With the ever increasing die sizes and the accompanied increase in the average global interconnect length, delay-optimal-routing and buffer-insertion techniques are significantly straining the power budget of modern ICs. To mitigate the impact of the power consumed by the interconnects and buffers, a power-efficient multipin routing technique is proposed in this paper. The problem is based on a graph representation of the routing possibilities, with the objective of identifying the minimum power path between the interconnect source and set of sinks. The technique is tested by applying it to the International Symposium on Physical Design and IBM benchmarks to verify the accuracy, complexity, and solution quality. Results obtained indicate that an average power saving as high as 32% for the 130-nm technology is achieved with no impact on the maximum chip frequency.

Comparative analysis of power yield improvement under process variation of sub-threshold flip-flops

Abstract: In low power synchronous systems, sub-threshold flip-flops are used to reduce the total power dissipation. Moreover, process variations create a large variability in the flip-flop power in scaled technologies impacting the power yield, especially, for sub-threshold operation. This paper presents an analysis of power yield improvement of four commonly used flip-flops under process variations. These flip-flops are designed using STMicroelectronics 65-nm CMOS technology. The analyzed flip-flops are compared for delay, energy, and energy-delay product (EDP) overheads to achieve this power yield improvement. The analysis shows that the sense amplifier based flip flop (SA-FF) has the lowest overheads while the modified clocked CMOS master slave flip-flop (M-C2MOS-MSFF) exhibits the largest overheads, and correspondingly, it is not recommended for sub-threshold operation.

Statistical timing yield improvement of dynamic circuits using negative capacitance technique

Abstract: Dynamic logic circuits are considered the best choice for high performance applications due to their relatively high speed. These high performance applications have strict timing constraints. Moreover, process variations create a large variability in the dynamic circuit delay in scaled technologies impacting the timing yield. In this paper, the negative capacitance is adopted, for the first time, for statistical timing yield improvement under process variations. Simulation results show that the adoption of the negative capacitance at the output of a 16-input dynamic NOR gate improves the timing yield by reducing the dynamic circuit delay. In addition, the negative capacitance adoption results in power saving of 10% and reduces the delay variability by 57.6%.

On the Power Management of Simultaneous Multithreading Processors

Abstract: Simultaneous multithreading (SMT) processors are widely used in high performance computing tasks However, with the improved performance of the SMT architecture, the utilization of their functional units is significantly increased, straining the power budget of the processor This increases not only the dynamic power consumption, but also the leakage power consumption due to the increased temperature In this paper, a comparison of the static and dynamic sleep signal generation techniques for SMT processors is presented This is conducted under various workloads to assess their effectiveness in leakage power management Results show that the dynamic approach exhibits a threefold increase in leakage savings, compared with that of the static approach for certain functional units

On the Power Management of

Abstract: Simultaneous multithreading (SMT) processors are widely used in high performance computing tasks. However, with the improved performance of the SMT architecture, the utilization of their functional units is significantly increased, straining the power budget of the processor. This increases not only the dynamic power consumption, but also the leakage power consumption due to the increased temperature. In this paper, a comparison of the static and dynamic sleep signal generation techniques for SMT processors is presented. This is conducted under var- ious workloads to assess their effectiveness in leakage power management. Results show that the dynamic approach exhibits a threefold increase in leakage savings, compared with that of the static approach for certain functional units.