M
Moinuddin K. Qureshi
Researcher at Georgia Institute of Technology
Publications - 144
Citations - 11625
Moinuddin K. Qureshi is an academic researcher from Georgia Institute of Technology. The author has contributed to research in topics: Cache & Computer science. The author has an hindex of 44, co-authored 131 publications receiving 9956 citations. Previous affiliations of Moinuddin K. Qureshi include IBM & University of Texas at Austin.
Papers
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Journal ArticleDOI
Accelerating Critical Section Execution with Asymmetric Multicore Architectures
TL;DR: The proposed accelerated critical sections mechanism reduces this limitation by executing critical sections on the high-performance core of an asymmetric chip multiprocessor, which can execute them faster than the smaller cores can.
Journal ArticleDOI
Refresh pausing in DRAM memory systems
TL;DR: Refresh Pausing exploits the property that each refresh operation in a typical DRAM device internally refreshes multiple DRAM rows in JEDEC-based distributed refresh mode and provides an average performance improvement of 5.1% for 8Gb devices and becomes even more effective for future high-density technologies.
Patent
Context look ahead storage structures
Philip G. Emma,Allan M. Hartstein,Brian R. Prasky,Thomas R. Puzak,Moinuddin K. Qureshi,Vijayalakshmi Srinivasan +5 more
TL;DR: In this paper, a memory storage structure includes a memory device, and a first meta-structure having a first size and operating at a first speed, where the second meta structure has a second size larger than the first and operates at a second speed such that faster and more accurate prefetching is provided by coaction of the first meta structure.
Patent
Apparatus and method for filtering unused sub-blocks in cache memories
TL;DR: In this article, a memory system and method includes a cache having a filtered portion and an unfiltered portion, where the filtered portion is divided into sub-block sized components.
Patent
Adaptive Wear Leveling via Monitoring the Properties of Memory Reference Stream
TL;DR: In this article, a write data stream is detected and a write leveling process is adapted in response to the detected property, and the write line addresses are generated from the detected properties.