M
Morgana M. A. da Rosa
Researcher at Universidade Católica de Pelotas
Publications - 16
Citations - 107
Morgana M. A. da Rosa is an academic researcher from Universidade Católica de Pelotas. The author has contributed to research in topics: Computer science & Adder. The author has an hindex of 2, co-authored 9 publications receiving 28 citations.
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Journal ArticleDOI
Design Methodology to Explore Hybrid Approximate Adders for Energy-Efficient Image and Video Processing Accelerators
Leonardo Bandeira Soares,Morgana M. A. da Rosa,Claudio Machado Diniz,Eduardo Costa,Sergio Bampi +4 more
TL;DR: This paper proposes a new design methodology to explore the state-of-the-art approximate adders for accelerator architectures conceived in the realm of multiplier-less multiple constant multiplication optimization problem.
Journal ArticleDOI
Approximate Pruned and Truncated Haar Discrete Wavelet Transform VLSI Hardware for Energy-Efficient ECG Signal Processing
Henrique Seidel,Morgana M. A. da Rosa,Guilherme Paim,Eduardo Costa,Sergio Almeida,Sergio Bampi +5 more
TL;DR: In this paper, an approximate Haar discrete wavelet transform (HDWT) hardware architecture for ECG processing at very high energy efficiency is presented. But, the authors do not consider the use of a truncation technique to improve energy efficiency.
Proceedings ArticleDOI
Exploring Efficient Adder Compressors for Power-Efficient Sum of Squared Differences Design
TL;DR: In this article, the 8-2 adder compressor in the addition tree of the Sum of Squared Differences (SSD) architecture is compared with the arithmetic operators automatically selected by the synthesis tool.
Proceedings ArticleDOI
The Radix-2 m Squared Multiplier
TL;DR: The radix-2m squared array multipliers (radix-4) as discussed by the authors is a general-purpose multipliers architecture that reduces the partial products by splitting the operands into mbit groups.
Proceedings ArticleDOI
Energy-Efficient Haar Transform Architectures Using Efficient Addition Schemes
Henrique Seidel,Morgana M. A. da Rosa,Guilherme Paim,Eduardo Costa,Sergio Almeida,Sergio Bampi +5 more
TL;DR: The results show that the Haar architecture with 4-2 and 5-2 compressors in the PM module, both with the recombination line with a Sklansky (SK) adder, is more efficient than the one using the tool-selected implementation of the behavioral "+" (sum) in VHDL, with 23% of power reduction.