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Guilherme Paim

Researcher at Universidade Federal do Rio Grande do Sul

Publications -  82
Citations -  474

Guilherme Paim is an academic researcher from Universidade Federal do Rio Grande do Sul. The author has contributed to research in topics: Adder & Computer science. The author has an hindex of 7, co-authored 60 publications receiving 201 citations. Previous affiliations of Guilherme Paim include Universidade Federal de Pelotas & Universidade Católica de Pelotas.

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Power-Efficient Sum of Absolute Differences Hardware Architecture Using Adder Compressors for Integer Motion Estimation Design

TL;DR: In this paper, the authors exploit different adder compressors structures into the SAD hardware architecture and synthesize an 8-2 compressor with 4-2 compressors and Kogge-Stone adder in the recombination line.
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A Cross-Layer Gate-Level-to-Application Co-Simulation for Design Space Exploration of Approximate Circuits in HEVC Video Encoders

TL;DR: The approach shows that the lower-part-or and error-tolerant adder I approximate adders, as well as truncation-to-zero deliver better compression-power trade-offs, with substantial differences from the static analysis.
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Approximate Pruned and Truncated Haar Discrete Wavelet Transform VLSI Hardware for Energy-Efficient ECG Signal Processing

TL;DR: In this paper, an approximate Haar discrete wavelet transform (HDWT) hardware architecture for ECG processing at very high energy efficiency is presented. But, the authors do not consider the use of a truncation technique to improve energy efficiency.
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Power-, Area-, and Compression-Efficient Eight-Point Approximate 2-D Discrete Tchebichef Transform Hardware Design Combining Truncation Pruning and Efficient Transposition Buffers

TL;DR: This work proposes a new approximation for the 8-point DTT, with a higher power- and compression-efficiency by exploring coefficient truncation, leading to the values 1/16, −1/ 16, 1/8, and −1/, and achieves higher compression ratio and less quality loss in the compressed image.
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On the Resiliency of NCFET Circuits Against Voltage Over-Scaling

TL;DR: In this paper, the authors investigated the resiliency of negative capacitance transistor (NCFET) technology to VOS in comparison to conventional CMOS technology and showed that the VOS-resilience of NCFET circuits enables maximizing the voltage decrease.