Showing papers in "IEICE Transactions on Electronics in 2011"

High power and stable high coupling efficiency (66%) superluminescent light emitting diodes by using active multi-mode interferometer

Abstract: The fabricated 1.55µm high power superluminescent light emitting diodes (SLEDs) with 115mW maximum output power and 3dB bandwidth of 50nm, using active multi-mode interferometer (MMI), showed high coupling efficiency of 66% into single-mode fiber, which resulted in maximum fiber-coupled power of 77mW.

Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using g m / I D Lookup Table Methodology

Abstract: We propose a design optimization flow for a high-speed and low-power operational transconductance amplifier (OTA) using a gm/ID lookup table design methodology in scaled CMOS. This methodology advantages from using gm/ID as a primary design parameter to consider all operation regions including strong, moderate, and weak inversion regions, and enables the lowest power design. SPICE-based lookup table approach is employed to optimize the operation region specified by the gm/ID with sufficient accuracy for short-channel transistors. The optimized design flow features 1) a proposal of the worst-case design scenario for specification and gm/ID lookup table generations from worst-case SPICE simulations, 2) an optimization procedure accomplished by the combination of analytical and simulation-based approaches in order to eliminate tweaking of circuit parameters, and 3) an additional use of gm/ID subplots to take second-order effects into account. A gain-boosted folded-cascode OTA for a switched capacitor circuit is adopted as a target topology to explore the effectiveness of the proposed design methodology for a circuit with complex topology. Analytical expressions of the gain-boosted folded-cascode OTA in terms of DC gain, frequency response and output noise are presented, and detailed optimization of gm/IDs as well as circuit parameters are illustrated. The optimization flow is verified for the application to a residue amplifier in a 10-bit 125MS/s pipeline A/D converter implemented in a 0.18µm CMOS technology. The optimized circuit satisfies the required specification for all corner simulations without additional tweaking of circuit parameters. We finally explore the possibility of applying this design methodology as a technology migration tool, and illustrate the failure analysis by comparing the differences in the gm/ID characteristics.

A Low-Power Real-Time SIFT Descriptor Generation Engine for Full-HDTV Video Recognition

Abstract: This paper describes a SIFT (Scale Invariant Feature Transform) descriptor generation engine which features a VLSI oriented SIFT algorithm, three-stage pipelined architecture and novel systolic array architectures for Gaussian filtering and key-point extraction. The ROI-based scheme has been employed for the VLSI oriented algorithm. The novel systolic array architecture drastically reduces the number of operation cycle and memory access. The cycle counts of Gaussian filtering module is reduced by 82%, compared with the SIMD architecture. The number of memory accesses of the Gaussian filtering module and the key-point extraction module are reduced by 99.8% and 66% respectively, compared with the results obtained assuming the SIMD architecture. The proposed schemes provide processing capability for HDTV resolution video (1920 × 1080 pixels) at 30 frames per second (fps). The test chip has been fabricated in 65nm CMOS technology and occupies 4.2 × 4.2mm2 containing 1.1M gates and 1.38Mbit on-chip memory. The measured data demonstrates 38.2mW power consumption at 78MHz and 1.2V.

Influence of Voltage on Arc Characteristics and Electrode Mass Change of AgNi Contacts for Electromagnetic Contactors

Abstract: NA

Fast Converging Measurement of MRC Diversity Gain in Reverberation Chamber Using Covariance-Eigenvalue Approach

Abstract: In this paper, we show that the covariance-eigenvalue approach converges much faster than using cumulative distribution function (CDF) for determining diversity gain from channel measurements in reverberation chamber. The covariance-eigenvalue approach can be used for arbitrary multi-port antennas, but it is limited to Maximum Ratio Combining (MRC).

A High-Efficiency Circularly-Polarized Aperture Array Antenna with a Corporate-Feed Circuit in the 60 GHz Band

Abstract: A circularly-polarized planar array antenna using hexagonal aperture elements is proposed. A 2×2-element subarray as the basic unit is excited by a corporate-feed circuit located in the lower layer of the double-layered antenna. The hexagonal aperture is designed to achieve a good axial ratio in the boresight. A 16×16-element array antenna with uniform element spacing smaller than the free-space wavelength was fabricated by diffusion bonding of laminated thin metal plates for the 60GHz-band. The high gain of 33.4dBic is measured with 91.6% antenna efficiency, including losses.

0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65nm CMOS

Abstract: In this paper, Digital Low Dropout Regulator (LDO) is proposed to provide the low noise and tunable power supply voltage to the 0.5-V near-threshold logic circuits. Because the conventional LDO feedback-controlled by the operational amplifier fail to operate at 0.5 V, the digital LDO eliminates all analog circuits and is controlled by digital circuits, which enables the 0.5-V operation. The developed digital LDO in 65 nm CMOS achieved the 0.5-V input voltage and 0.45-V output voltage with 98.7% current efficiency and 2.7-μA quiescent current at 200-μA load current. Both the input voltage and the quiescent current are the lowest values in the published LDO's, which indicates the good energy efficiency of the digital LDO at 0.5-V operation.

A 35-GHz, 0.8-A/W and 26-µm Misalignment Tolerance Microlens-Integrated p-i-n Photodiodes

Abstract: We fabricated a p-i-n photodiode (PD) with an integrated microlens, and demonstrated its high performance capabilities including high speed (35GHz), high responsivity (0.8A/W), and large misalignment tolerance (26µm), and an error-free 25-Gbit/s 10-km single-mode fiber transmission by using a 100-Gbit/s Ethernet quadplexer receiver module with the PDs.

Analysis of a New High-Speed DC Switch Repulsion Mechanism

Abstract: This paper focuses on the research of a new high-speed DC switch repulsion mechanism with experimental and simulation methods. Multi-physical equations reflecting the transient electromagnetic field, electric circuit, mechanical motion and material deformation are coupled in the calculation. For the reason of accuracy, skin effect and the proximity effect caused by the current in the coil are also taken into account. According to the simulation results, which indicate several key parameters severely affecting the mechanism speed, a high-speed DC switch repulsion mechanism is developed. By the test of mechanism motion, its average speed can be up to 8.4m/s and its mechanism response time is 250µs, which verifies the simulation results. Furthermore, during high speed motion the stress on the metal plate and moving contact is also discussed. It is noticed that the influence of the material deformation on the mechanical motion is very important.

Reflection, Diffraction and Scattering at Low Grazing Angle of Incidence: Regular and Random Systems

Abstract: When a monochromatic electromagnetic plane wave is incident on an infinitely extending surface with the translation invariance property, a curious phenomenon often takes place at a low grazing angle of incidence, at which the total wave field vanishes and a dark shadow appears. This paper looks for physical and mathematical reasons why such a shadow occurs. Three cases are considered: wave reflection by a flat interface between two media, diffraction by a periodic surface, and scattering from a homogeneous random surface. Then, it is found that, when a translation invariant surface does not support guided waves (eigen functions) propagating with real propagation constants, such the shadow always takes place, because the primary excitation disappears at a low grazing angle of incidence. At the same time, a shadow form of solution is proposed. Further, several open problems are given for future works.

Loss of Post-Wall Waveguides and Efficiency Estimation of Parallel-Plate Slot Arrays Fed by the Post-Wall Waveguide in the Millimeter-Wave Band

Abstract: This paper presents the loss factors in the post-wall waveguide-fed parallel-plate slot array antenna in the millimeter-wave band At first, transmission loss is evaluated per unit length by measuring the losses of post-wall waveguides on various substrates with different thicknesses in different bands Measured results of the frequency dependence agree with theoretical predictions using the effective conductivity and the complex permittivity obtained by the whispering gallery mode resonator method Then the authors evaluate the antennas with various sizes at 765 GHz The antenna efficiency is evaluated by taking into account the loss factors related to: the transmission loss both in the feed and the parallel plate waveguides, the aperture efficiency and the insertion loss and the reflection of the transition Also, the loss due to the locally-perturbed currents by the slot radiation is evaluated The sum of the losses in the prediction quantitatively agrees with the measurement

Remarks on Transient Amplitude Analysis of MOS Cross-Coupled Oscillators

Abstract: In this paper, closed-form analytical equations for the time-domain amplitude of the MOS cross-coupled oscillators are derived. The procedure of the paper is based on estimating an accurate equation for describing the behavior of the cross-coupled MOS configurations and finding a reasonable solution for the nonlinear differential equation governing the circuit. The solution method is presented for a general equation and is valid for all possible second-order oscillators. Both of the long channel and short channel transistor topologies have been investigated. The resulted equations are in a good agreement with simulation results for a wide range of the circuit parameters and enable us to analyze and synthesize the oscillators with the desired transient behavior.

Scattering of a Plane Wave from the End-Face of a Three-Dimensional Waveguide System

Abstract: The scattering of a plane wave from the end-face of a three-dimensional waveguide system composed of a large number of cores is treated by the volume integral equation for the electric field and the first order term of a perturbation solution for TE and TM wave incidence is analytically derived. The far scattered field does not almost depend on the polarization of an incident wave and the angle dependence is described as the Fourier transform of the incident field in the cross section of cores. To clarify the dependence of the scattering pattern on the arrangement of cores some numerical examples are shown.

Proposal of a Compact Neutron Diffraction System with a Single-Flux-Quantum Signal Processor

Abstract: We propose a neutron diffractometer system based on MgB2 thin film detectors and an SFQ signal processor. Small dimensions of MgB2 thin film detectors and high processing capability of the single flux quantum (SFQ) circuits enable us to handle several thousand or more detectors in a cryocooler, leading to a very compact system. In addition, the system can provide many diffraction patterns for different kinetic energies simultaneously. Kinetic energy is determined for individual neutrons by means of the time-of-flight method by using SFQ time-to-digital converters (TDCs). Digital outputs of the TDCs are multiplexed in time domain and sent to room-temperature electronics with reduced number of cables. A dual-input SFQ signal processor including TDCs and a multiplexer has been successfully demonstrated with a time resolution of 20ns and power consumption of 400μW. These values show high feasibility of the neutron diffraction system proposed here.

A 2 Gb/s 1.8 pJ/bit Differential BPSK UWB-IR Transmitter Using 65 nm CMOS Technology

Abstract: A differential BPSK transmitter for ultra-wideband impulse-radio communication has been presented in this paper. The transmitter, developed in a 65 nm CMOS process,is simple in design and occupies a core area of 0.0017 mm 2 . The differential Gaussian monocycle pulses (GMP) are generated using some logic blocks and delay elements. The generated GMP, having a center frequency above 5 GHz, meets the FCC regulations. Measured results show that the transmitter consumes 1.8 pJ/bit to transmit BPSK modulated GMP at a data rate of 2 Gb/s. The interface circuitries eliminate the need for external networks for chip to antenna matching. Using an off-chip differential bow-tie antenna, data can easily be transmitted up to a distance of 10 cm which made it suitable for low power far field non-coherent applications.

Random Occurrence of Contact Welding in Electrical Endurance Tests

Abstract: To clarify how the occurrence of contact welding is related to the series of arc duration characteristics in consecutive make and break operations, electrical endurance tests were conducted on commercially available automotive relays, and the voltage waveforms of make and break arcs between the electrodes were recorded with LabVIEW. Experimental results indicate that welding may occur suddenly or randomly with increasing number of operations. A single arc or a group of make or break arcs with a long arc duration does not necessarily result in contact welding, but a group of longer make or break arcs within a narrow range of operation numbers can cause imminent contact welding (such an effect can be called the “group of longer arcing duration effect”). It is confirmed that contact welding may occur in both make and break operations, but the welding probability during make operations is much higher than that during break operations.

Built-In Measurements in Low-Cost Digital-RF Transceivers

Abstract: Digital RF solutions have been shown to be advantageous in various design aspects, such as accurate modeling, design reuse, and scaling when migrating to the next CMOS process node. Consequently, the majority of new low-cost and feature cell phones are now based on this approach. However, another equally important aspect of this approach to wireless transceiver SoC design, which is instrumental in allowing fast and low-cost productization, is in creating the inherent capability to assess performance and allow for low-cost built-in calibration and compensation, as well as characterization and final-testing. These internal capabilities can often rely solely on the SoCs existing processing resources, representing a zero cost adder, requiring only the development of the appropriate algorithms. This paper presents various examples of built-in measurements that have been demonstrated in wireless transceivers offered by Texas Instruments in recent years, based on the digital-RF processor (DRPTM) technology, and highlights the importance of the various types presented; built-in self-calibration and compensation, built-in self-characterization, and built-in self-testing (BiST). The accompanying statistical approach to the design and productization of such products is also discussed, and fundamental terms related with these, such as ‘soft specifications’, are defined.

Current Status of Josephson Arbitrary Waveform Synthesis at NMIJ/AIST

Abstract: AC-waveform synthesis with quantum-mechanical accuracy has been attracting many researchers, especially metrologists in national metrology institutes, not only for its scientific interest but its potential benefit to industries. We describe the current status at National Metrology Institute of Japan of development of a Josephson arbitrary waveform synthesizer based on programmable and pulse-driven Josephson junction arrays.

Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits

Abstract: In this paper, we propose a method for layout-driven skewed clock tree synthesis for SFQ logic circuits. For a given logic circuit without a clock tree, our algorithm outputs a circuit with a synthesized clock tree and timing adjustments achieving the given clock period and a rough placement of the clocked gates. In the proposed algorithm, clocked gates are grouped into levels and the clock tree is synthesized for each level. For each level, we estimate the clock timing for all possible placements of each gate, and then we search a placement of all gates that minimizes the total number of delay elements for timing adjustment. Once the placement is obtained, we synthesize a clock tree without wire intersections. We applied the proposed method to a moderate size circuit and confirmed that clock trees satisfying given timing requirements can be synthesized automatically.

Eigenmode Analysis of Propagation Constant for a Microstrip Line with Dummy Fills on a Si CMOS Substrate

Abstract: In this paper we present eigenmode analysis of the propagation constant for a microstrip line with dummy fills on a Si CMOS substrate. The effect of dummy fills is not negligible, particularly in the millimeter-wave band, although it has been ignored below frequencies of a few GHz. The propagation constant of a microstrip line with a periodic structure on a Si CMOS substrate is analyzed by eigenmode analysis for one period of the line. The calculated propagation constant and characteristic impedance were compared with measured values for a chip fabricated by the 0.18 μm CMOS process. The agreement between the analysis and measurement was very good. The dependence of loss on the arrangement of dummy fills was also investigated by eigenmode analysis. It was found that the transmission loss becomes large when dummy fills are arranged at places where the electromagnetic field is strong.

Effect of Heat Conductivity on Bridge Break at Different Material Contact Pairs

Abstract: In this paper, to clarify the thermal effect of the bridge for long lifetime contacts, the effects of heat conductivity on bridge break at different material contact pairs were discussed experimentally To examine the relationship between the bridge and material, the electrode materials of the anode and the cathode were chosen as the same and the different material pairs in this experiment Ag, AgPd60 and Pd were chosen as the electrode materials, because Ag, AgPd60 and Pd had the different thermal diffusivity Firstly, the voltage waveforms in the bridge with different material pair were compared to the voltage waveform with the same material pair case Secondary, the effects of heat conductivity on the break of bridge were discussed In the results, the bridge voltage waveform depends on the electrode material at anode side The length of the bridge at bridge break depends on the heat conductivity of the electrode material at anode side This study provides the basic considerations on the thermal condition of the bridge break

A 500 MS/s 600 µW 300 µm 2 Single-Stage Gain-Improved and Kickback Noise Rejected Comparator in 0.35 µm 3.3 v CMOS Process

Abstract: This paper presents a high speed single-stage latched comparator which is scheduled in time for both amplification and latch operations. Small active area and simple switching strategy besides desired power consumption at high comparison rates qualifies the proposed comparator to be repeatedly employed in high speed flash A/D converters. A strategy of kickback noise elimination besides gain enhancement is also introduced. A low power holding read-out circuit is presented. Post-Layout simulation results confirm 500MS/s comparison rate with 5mv resolution for a 1.6v peak-to-peak input signal range and 600µw power consumption from a 3.3v power supply by using TSMC model of 0.35µm CMOS technology. Total active area of proposed comparator and read-out circuit is about 300µm2.

Design of a Broadband Cruciform Substrate Integrated Waveguide Coupler

Abstract: A broadband cruciform substrate integrated waveguide coupler is designed based on the planar circuit approach. The broadband property is obtained by widening the crossed region in the same way as rectangular waveguide cruciform couplers. As a result, a 3dB coupler with fractional bandwidth of 30% is realized at 24GHz.

Monolithically Integrated Wavelength-Routing Switch Using Tunable Wavelength Converters with Double-Ring-Resonator Tunable Lasers

Abstract: We present an 8×8 wavelength-routing switch (WRS) that monolithically integrates tunable wavelength converters (TWCs) and an 8×8 arrayed-waveguide grating The TWC consists of a double-ring-resonator tunable laser (DRR TL) allowing rapid and stable switching and a semiconductor-optical-amplifier-based optical gate Two different types of dry-etched mirrors form the laser cavity of the DRR TL, which enable integration of the optical components of the WRS on a single chip The monolithic WRS performed 1×8 high-speed wavelength routing of a non-return-to-zero signal at 10Gbit/s The switching operation was demonstrated by simultaneously using two adjacent TWCs

Inverse Distance Weighting Method Based on a Dynamic Voronoi Diagram for Thermal Reconstruction with Limited Sensor Data on Multiprocessors

Abstract: With exponentially increasing power densities due to technology scaling and ever increasing demand for performance, chip temperature has become an important issue that limits the performance of computer systems. Typically, it is essential to use a set of on-chip thermal sensors to monitor temperatures during the runtime. The runtime thermal measurements are then employed by dynamic thermal management techniques to manage chip performance appropriately. In this paper, we propose an inverse distance weighting method based on a dynamic Voronoi diagram for the reconstruction of full thermal characterization of integrated circuits with non-uniform thermal sensor placements. Firstly we utilize the proposed method to transform the non-uniformly spaced samples to virtual uniformly spaced data. Then we apply three classical interpolation algorithms to reconstruct the full thermal signals in the uniformly spaced samples mode. To evaluate the effectiveness of our method, we develop an experiment for reconstructing full thermal status of a 16-core processor. Experimental results show that the proposed method significantly outperforms spectral analysis techniques, and can obtain full thermal characterization with an average absolute error of 1.72% using 9 thermal sensors per core.

Design for Testability That Reduces Linearity Testing Time of SAR ADCs

Abstract: This brief paper describes design-for-testability (DFT) circuitry that reduces testing time and thus cost of testing DC linearity of SAR ADCs. We present here the basic concepts, an actual SAR ADC chip design employing the proposed DFT, as well as measurements that verify its effectiveness. Since the DFT circuit overhead is small, it is practicable.

Modulation of PtSi Work Function by Alloying with Low Work Function Metal

Abstract: In order to reduce PtSi Schottky barrier height (SBH) for electron, we investigated modulation of PtSi work function by alloying with low work function metal, such as Hf (3.9eV) and Yb (2.7eV). Pt (10-20nm)/Hf, Yb (0-10nm)/n-Si(100) stacked structures were in-situ deposited at room temperature by RF magnetron sputtering method. In case of PtxHf1-xSi formed at 400°C/60min annealing in N2, SBH for electron was reduced from 0.85eV to 0.53eV with Hf thickness without increase of sheet resistance. Yb incorporation also affected the SBH modulation, however, the sheet resistance increased with increase of Yb thickness.

A New Miniaturization and the nth Harmonic Suppression of Wilkinson Power

Abstract: In this article, a simple structure of the Wilkinson power divider which can suppress the nth harmonics of the Wilkinson power divider is proposed. By replacing the quarter wavelength transmission lines of the conventional Wilkinson power divider with the equivalent P-type transmission lines, a compact power divider which can suppress the nth harmonic is achieved. Design equations of proposed P-type line are achieved by ABCD matrices. To verify the design approach, the proposed power divider is designed, simulated (by ADS, CST Studio, and Sonnet simulators), and fabricated at 1 GHz to suppress the fifth harmonic. The proposed structure is 46% of the conventional Wilkinson power divider, while maintaining the characteristics of the conventional Wilkinson power divider at the fundamental frequency. The insertion losses at the fifth harmonic are larger than 35 dB. Furthermore, the second to seventh harmonic are suppressed by least 10dB. Here is an excellent agreement between simulated results and measured results.

0.18-V Input Charge Pump with Forward Body Bias to Startup Boost Converter for Energy Harvesting Applications

Abstract: In this paper, a 018-V input three-stage charge pump circuit applying forward body bias is proposed for energy harvesting applications In the developed charge pump, all the MOSFETs are forward body biased by using the inter-stage/output voltages By applying the proposed charge pump as the startup in the boost converter, the kick-up input voltage of the boost converter is reduced to 018V To verify the circuit characteristics, the conventional zero body bias charge pump and the proposed forward body bias charge pump were fabricated with 65nm CMOS process The measured output current of the proposed charge pump under 018-V input voltage is increased by 170% comparing to the conventional one at the output voltage of 05V In addition, the boost converter successfully boosts the 018-V input to higher than 065-V output