In recent days, increasing numbers of Internet and wireless network users have helped accelerate the need for encryption mechanisms and devices to protect user data sharing across an unsecured network. Data security, integrity, and verification may be used due to these features. In internet traffic encryption, symmetrical block chips play an essential role. Data Encryption Standard (DES) and Advanced Encryption Standard (AES) ensure privacy encryption underlying data protection standards. The DES and the AES provide information security. DES and AES have the distinction of being introduced in both hardware and applications. DES and AES hardware implementation has many advantages, such as increased performance and improved safety. This paper provides an exhaustive study of the implementation by DES and AES of field programming gate arrays (FPGAs) using both DES and AES. Since FPGAs can be defined as just one mission, computers are superior to them.

https://journal.qubahan.com/index.php/qaj/article/download/38/22

FPGA Implementations for Data Encryption and Decryption via Concurrent and Parallel Computation: A Review

Electrocardiogram (ECG) monitoring systems are widely applied to tele-cardiology healthcare programs nowadays, where ECG signals should always be compressed first during its transmission and storage. Previous studies attempted to achieve high quality decompressed signal with compression ratio as high as possible. In this paper, we investigated the performance on ECG arrhythmia classification on ECG signal decompressed after lossy compression with a high compression ratio. We proposed a simple but efficient method utilizing singular value decomposition (SVD) to decompose ECG signals, then applied the decompressed data to a convolutional neural network (CNN) and supporting vector machine (SVM) for classification. Using the optimization method with accuracy and compression ratio as objective functions, the highest average accuracy obtained is above 96% when the selected number of singular value is only 3. The evaluation results illustrated that the decompressed ECG signal even with a relatively high distortion can still achieve a satisfying performance in the arrhythmia classification.Thus,we proved that the real-time nature of the remote mobile ECG monitoring system can be greatly improved and countless people who are in need of ECG diagnosis can benefit from it.

Effective compression and classification of ECG arrhythmia by singular value decomposition

Assessment of drinking water quality has been an important issue nowadays as the water available is severely polluted and can be the cause of diseases like cholera, diarrhea, dysentery, etc. The traditional methods for water quality monitoring require a high-labor-cost and tine consumption as these methods include a sample collection followed by lab-based chemical testing. In addition, the chemicals used in the testing are toxic and of high-cost. So, there is a need for real-time monitoring and chemical-free testing of water quality parameters. This paper presents a real-time water quality monitoring system based on the Raspberry Pi 3 development board and a Python framework. The water quality parameters utilized for water quality monitoring are temperature, pH, oxidation reduction potential, electrical conductivity, and dissolved oxygen and E. coli. The water quality sensors were interfaced with the designed embedded platform. Finally, the acquired parameters were compared with the benchmark equipment for validation.

https://link.springer.com/content/pdf/10.1007/s42979-020-00368-9.pdf

Assessment of Water Quality Parameters in Real-Time Environment

6G Communication Networks: Introduction, Vision, Challenges, and Future Directions

The RFID Technology is widely used in many authentications and a sophisticated application, still having many prospective issues includes privacy and security issues. To resolve these issues, this paper presents an efficient Lightweight cryptographic Block cipher algorithm. The hardware architecture of Tiny Encryption Algorithm (TEA) is designed and which is simple, flexible, fewer computations required and simple key scheduling. To overcome the security attacks in key scheduling on TEA, an Extended TEA (XTEA) is designed, which is having pipelined architecture with parallel computation to improve the throughput and provide better security. The proposed XTEA is in reconfigurable nature, by changing the mode to process encryption or decryption. The TEA and XTEA simulation results are obtained from Xilinx ISE tool on ModelSim 6.5f simulator and implemented on FPGA Platform-Artix-7 with resource constraints like Area, time and power are tabulated. The proposed XTEA is compared with similar existing research approaches like AES-8bit, TinyXTEA1, and Tiny XTEA-3 with an improvement of Area, throughput and Efficiency on same FPGA platform. The proposed XTEA works at the high throughput of 81 Mbps and Efficiency of 0.34 Mbps/Slice.

LCBC-XTEA: High Throughput Lightweight Cryptographic Block Cipher Model for Low-Cost RFID Systems

In recent years, wireless vision sensor network (WVSN) is being used to retrieve video content from different image sensors which are connected to different devices wirelessly. This information is used to do video analysis which can help to automate different tasks such as video surveillance. For such systems, power consumption during processing and communicating information has been a challenge because of limited energy sources at the node. To deal with the energy consumption problem, in this paper WVSN is proposed with its algorithm and hardware implementation for a smart home application. The computation tasks have been divided between the sensor node and the central server. While taking care of privacy issues during the transmission of data, a low complexity system has been developed for sensor nodes. For video analysis, foreground segmentation, object labeling, and object tracking have been performed. An efficient binary data compression technique has been proposed to compress the information during the labeling process. The proposed system has a high recognition rate for gesture recognition and human tracking. The system can achieve eight frames per second during processing information on Raspberry Pi board. This system can be extended further to include other smart home applications.

/pdf/design-of-wireless-vision-sensor-network-for-smart-home-2b7jasv1a8.pdf

Design of Wireless Vision Sensor Network for Smart Home

Deep neural networks are widely used in computer vision applications due to their high performance. However, DNNs involve a large number of computations in the training and inference phase. Among the different layers of a DNN, the softmax layer has one of the most complex computations as it involves exponent and division operations. So, a hardware-efficient implementation is required to reduce the on-chip resources. In this paper, we propose a new hardware-efficient and fast implementation of the softmax activation function. The proposed hardware implementation consumes fewer hardware resources and works at high speed as compared to the state-of-the-art techniques.

An Efficient and Fast Softmax Hardware Architecture (EFSHA) for Deep Neural Networks

Transmission of sensitive data over some channel is a highly security constrained scenario and thus demands the application of some encryption algorithm. It is better to implement the algorithm in hardware as compared to software due to better computational speed and memory usage. Tiny Encryption Algorithm known as TEA block cipher is a light-weight and efficient cryptographic algorithm, well suited for wireless communication systems. This paper presents the successful implementation of TEA on FPGA for different design approaches to analyze the performance and resource utilization against each design approach.

FPGA Based Implementation Scenarios of TEA Block Cipher

This brief presents a VLSI implementation of an efficient lossless compression scheme for electrocardiogram (ECG) data encoding to save storage space and reduce transmission time. As compression algorithm is able to save storage space and reduce transmission time, this opportunity has been seized by implementing memory-less design while working at a high clock speed in VLSI. ECG compression algorithm comprises two parts: an adaptive linear prediction technique and content-adaptive Golomb Rice code. An efficient and low power VLSI implementation of compression algorithm has been presented. To improve the performance, the proposed VLSI design uses bit shifting operations as a replacement for the different arithmetic operations. VLSI implementation has been applied to the MIT-BIH arrhythmia database which is able to achieve a lossless bit compression rate of 2.77. Moreover, VLSI architecture contains 3.1 K gate count and core of the chip consumes 27.2 nW of power while working at 1 KHz frequency. The core area is 0.05 mm2 in 90 nm CMOS process.

VLSI Implementation of Lossless ECG Compression Algorithm for Low Power Devices

Training of Deep Neural Network (DNN) at the edge faces the challenge of high energy consumption due to the requirements of a large number of memory accesses for gradient calculations. Therefore, it is necessary to minimize data fetches to perform training of a DNN model on the edge. In this paper, a novel technique has been proposed to reduce the memory access for the training of fully connected layers in transfer learning. By analyzing the memory access patterns in the backpropagation phase in fully connected layers, the memory access can be optimized. We introduce a new method to update the weights by introducing the delta term for every node of output and fully connected layer. Delta term aims to reduce memory access for the parameters which are required to access repeatedly during the training process of fully connected layers. The proposed technique shows 0.13x-13.93x energy savings for the training of fully connected layers for famous DNN architectures on multiple processor architectures. The proposed technique can be used to perform transfer learning on-chip to reduce energy consumption as well as memory access.

Muhammad Awais Hussain

Papers

Design of Wireless Vision Sensor Network for Smart Home

An Efficient and Fast Softmax Hardware Architecture (EFSHA) for Deep Neural Networks

FPGA Based Implementation Scenarios of TEA Block Cipher

VLSI Implementation of Lossless ECG Compression Algorithm for Low Power Devices

Memory Access Optimization for On-Chip Transfer Learning