Showing papers by "Muhammad Mustafa Hussain published in 2012"

Vertically grown multiwalled carbon nanotube anode and nickel silicide integrated high performance microsized (1.25 μL) microbial fuel cell.

Abstract: Microbial fuel cells (MFCs) are an environmentally friendly method for water purification and self-sustained electricity generation using microorganisms. Microsized MFCs can also be a useful power source for lab-on-a-chip and similar integrated devices. We fabricated a 1.25 μL microsized MFC containing an anode of vertically aligned, forest type multiwalled carbon nanotubes (MWCNTs) with a nickel silicide (NiSi) contact area that produced 197 mA/m2 of current density and 392 mW/m3 of power density. The MWCNTs increased the anode surface-to-volume ratio, which improved the ability of the microorganisms to couple and transfer electrons to the anode. The use of nickel silicide also helped to boost the output current by providing a low resistance contact area to more efficiently shuttle electrons from the anode out of the device.

Are Nanotube Architectures More Advantageous Than Nanowire Architectures For Field Effect Transistors

Abstract: Decade long research in 1D nanowire field effect transistors (FET) shows although it has ultra-low off-state leakage current and a single device uses a very small area, its drive current generation per device is extremely low. Thus it requires arrays of nanowires to be integrated together to achieve appreciable amount of current necessary for high performance computation causing an area penalty and compromised functionality. Here we show that a FET with a nanotube architecture and core-shell gate stacks is capable of achieving the desirable leakage characteristics of the nanowire FET while generating a much larger drive current with area efficiency. The core-shell gate stacks of silicon nanotube FETs tighten the electrostatic control and enable volume inversion mode operation leading to improved short channel behavior and enhanced performance. Our comparative study is based on semi-classical transport models with quantum confinement effects which offers new opportunity for future generation high performance computation.

Cylindrical-shaped nanotube field effect transistor

Abstract: A cylindrical-shaped nanotube FET may be manufactured on silicon (Si) substrates as a ring etched into a gate stack and filled with semiconductor material. An inner gate electrode couples to a region of the gate stack inside the inner circumference of the ring. An outer gate electrode couples to a region of the gate stack outside the outer circumference of the ring. The multi-gate cylindrical-shaped nanotube FET operates in volume inversion for ring widths below 15 nanometers. The cylindrical-shaped nanotube FET demonstrates better short channel effect (SCE) mitigation and higher performance (I on /I off ) than conventional transistor devices. The cylindrical- shaped nanotube FET may also be manufactured with higher yields and cheaper costs than conventional transistors.

Nano-materials Enabled Thermoelectricity from Window Glasses

Abstract: With a projection of nearly doubling up the world population by 2050, we need wide variety of renewable and clean energy sources to meet the increased energy demand. Solar energy is considered as the leading promising alternate energy source with the pertinent challenge of off sunshine period and uneven worldwide distribution of usable sun light. Although thermoelectricity is considered as a reasonable renewable energy from wasted heat, its mass scale usage is yet to be developed. Here we show, large scale integration of nano-manufactured pellets of thermoelectric nano-materials, embedded into window glasses to generate thermoelectricity using the temperature difference between hot outside and cool inside. For the first time, this work offers an opportunity to potentially generate 304 watts of usable power from 9 m2 window at a 20°C temperature gradient. If a natural temperature gradient exists, this can serve as a sustainable energy source for green building technology.

(110) and (100) Sidewall-oriented FinFETs: A performance and reliability investigation

Abstract: The performance and reliability of (1 0 0) and (1 1 0) sidewall, silicon-on-insulator (SOI) FinFETs with a Hf-based gate dielectric were evaluated. Unlike the typical planar MOSFET mobility orientation dependence, (1 1 0) FinFET sidewalls do not impair electron mobility and result in good short channel performance compared to (1 0 0) FinFET sidewall devices. Hot carrier injection (HCI) degradation was also investigated with nMOS and pMOS high-κ FinFETs on both sidewall surface orientations. Impact ionization at the source, as well as at the traditional drain side, was found to enhance HCI degradation when gate voltage ( V g ) = drain voltage ( V d ). The degradation becomes more pronounced as the gate length decreases, with a negligible dependence on substrate orientation. However, the orientation dependence of negative bias temperature instability (NBTI) on FinFETs demonstrates that the (1 1 0) orientation is slightly worse than (1 0 0). The kinetics of Δ N IT ( t ) under negative bias stress conditions suggests the interface trap density ( N IT ) is generated by a mechanism similar to that in planar devices.

Mechanically flexible optically transparent porous mono-crystalline silicon substrate

Abstract: For the first time, we present a simple process to fabricate a thin (>5Lim), mechanically flexible, optically transparent, porous mono-crystalline silicon substrate. Relying only on reactive ion etching steps, we are able to controllably peel off a thin layer of the original substrate. This scheme is cost favorable as it uses a low-cost silicon wafer and furthermore it has the potential for recycling the remaining part of the wafer that otherwise would be lost and wasted during conventional back-grinding process. Due to its porosity, it shows see-through transparency and potential for flexible membrane applications, neural probing and such. Our process can offer flexible, transparent silicon from post high-thermal budget processed device wafer to retain the high performance electronics on flexible substrates.

Integrated circuit manufacturing for low-profile and flexible devices

Abstract: A process for manufacturing low-profile and flexible integrated circuits includes manufacturing an integrated circuit on a wafer having a thickness larger than the desired thickness. After the integrated circuit is manufactured the integrated circuit may be released with a portion of the wafer leaving a remainder of the bulk portion of the wafer. A second integrated circuit may be manufactured on the remainder of the wafer and the process repeated to manufacture additional integrated circuits from a single wafer. The integrated circuits may be released from the wafer by etching vias through the integrated circuit and into the wafer. The via may be used to start an etch process inside the wafer that undercuts the integrated circuit separating the integrated circuit from the wafer.

Method for producing mechanically flexible silicon substrate

Abstract: A method for making a mechanically flexible silicon substrate is disclosed. In one embodiment, the method includes providing a silicon substrate. The method further includes forming a first etch stop layer in the silicon substrate and forming a second etch stop layer in the silicon substrate. The method also includes forming one or more trenches over the first etch stop layer and the second etch stop layer. The method further includes removing the silicon substrate between the first etch stop layer and the second etch stop layer.

Contact engineering for nano-scale CMOS

Abstract: High performance computation with longer battery lifetime is an essential component in our today's digital electronics oriented life. To achieve these goals, field effect transistors based complementary metal oxide semiconductor play the key role. One of the critical requirements of transistor structure and fabrication is efficient contact engineering. To catch up with high performance information processing, transistors are going through continuous scaling process. However, it also imposes new challenges to integrate good contact materials in a small area. This can be counterproductive as smaller area results in higher contact resistance thus reduced performance for the transistor itself. At the same time, discovery of new one or two-dimensional materials like nanowire, nanotube, or atomic crystal structure materials, introduces new set of challenges and opportunities. In this paper, we are reviewing them in a synchronized fashion: fundamentals of contact engineering, evolution into non-planar field effect transistors, opportunities and challenges with one and two-dimensional materials and a new opportunity of contact engineering from device architecture perspective.

Sub-15 nm nano-pattern generation by spacer width control for high density precisely positioned self-assembled device nanomanufacturing

Abstract: We present a conventional micro-fabrication based thin film vertical sidewall (spacer) width controlled nano-gap fabrication process to create arrays of nanopatterns for high density precisely positioned self-assembled nanoelectronics device integration. We have used conventional optical lithography to create base structures and then silicon nitride (Si 3 N 4 ) based spacer formation via reactive ion etching. Control of Si 3 N 4 thickness provides accurate control of vertical sidewall (spacer) besides the base structures. Nano-gaps are fabricated between two adjacent spacers whereas the width of the gap depends on the gap between two adjacent base structures minus width of adjacent spacers. We demonstrate the process using a 32 nm node complementary metal oxide semiconductor (CMOS) platform to show its compatibility for very large scale heterogeneous integration of top-down and bottom-up fabrication as well as conventional and selfassembled nanodevices. This process opens up clear opportunity to overcome the decade long challenge of high density integration of self-assembled devices with precise position control.

Excellent endurance of MWCNT anode in micro-sized Microbial Fuel Cell

Abstract: Microbial Fuel Cells (MFCs) are a sustainable technology for energy production using bioelectrochemical reactions from bacteria. Microfabrication of micro-sized MFCs allows rapid and precise production of devices that can be integrated into Lab-on-a-chip or other ultra low power devices. We show a multi-walled carbon nanotubes (MWCNTs) integrated anode in a biocompatible and high power and current producing device. Long term testing of the MWCNT anode also reveals a high endurance and durable anode material that can be adapted as a long-lasting power source.