To support bursty traffic on the Internet (and especially WWW) efficiently, optical burst switching (OBS) is proposed as a way to streamline both protocols and hardware in building the future gener...

Optical burst switching (OBS) - a new paradigm for an optical Internet

Hierarchies arise in the context of access control whenever the user population can be modeled as a set of partially ordered classes (represented as a directed graph). A user with access privileges for a class obtains access to objects stored at that class and all descendant classes in the hierarchy. The problem of key management for such hierarchies then consists of assigning a key to each class in the hierarchy so that keys for descendant classes can be obtained via efficient key derivation.We propose a solution to this problem with the following properties: (1) the space complexity of the public information is the same as that of storing the hierarchy; (2) the private information at a class consists of a single key associated with that class; (3) updates (i.e., revocations and additions) are handled locally in the hierarchy; (4) the scheme is provably secure against collusion; and (5) each node can derive the key of any of its descendant with a number of symmetric-key operations bounded by the length of the path between the nodes. Whereas many previous schemes had some of these properties, ours is the first that satisfies all of them. The security of our scheme is based on pseudorandom functions, without reliance on the Random Oracle Model.Another substantial contribution of this work is that we are able to lower the key derivation time at the expense of modestly increasing the public storage associated with the hierarchy. Insertion of additional, so-called shortcut, edges, allows to lower the key derivation to a small constant number of steps for graphs that are total orders and trees by increasing the total number of edges by a small asymptotic factor such as O(log*n) for an n-node hierarchy. For more general access hierarchies of dimension d, we use a technique that consists of adding dummy nodes and dimension reduction. The key derivation work for such graphs is then linear in d and the increase in the number of edges is by the factor O(logd − 1n) compared to the one-dimensional case.Finally, by making simple modifications to our scheme, we show how to handle extensions proposed by Crampton [2003] of the standard hierarchies to “limited depth” and reverse inheritance.

Dynamic and Efficient Key Management for Access Hierarchies

We present a new design for a 1-b full adder featuring hybrid-CMOS design style. The quest to achieve a good-drivability, noise-robustness, and low-energy operations for deep submicrometer guided our research to explore hybrid-CMOS style design. Hybrid-CMOS design style utilizes various CMOS logic style circuits to build new full adders with desired performance. This provides the designer a higher degree of design freedom to target a wide range of applications, thus significantly reducing design efforts. We also classify hybrid-CMOS full adders into three broad categories based upon their structure. Using this categorization, many full-adder designs can be conceived. We will present a new full-adder design belonging to one of the proposed categories. The new full adder is based on a novel xor-xnor circuit that generates xor and xnor full-swing outputs simultaneously. This circuit outperforms its counterparts showing 5%-37% improvement in the power-delay product (PDP). A novel hybrid-CMOS output stage that exploits the simultaneous xor-xnor signals is also proposed. This output stage provides good driving capability enabling cascading of adders without the need of buffer insertion between cascaded stages. There is approximately a 40% reduction in PDP when compared to its best counterpart. During our experimentations, we found out that many of the previously reported adders suffered from the problems of low swing and high noise when operated at low supply voltages. The proposed full adder is energy efficient and outperforms several standard full adders without trading off driving capability and reliability. The new full-adder circuit successfully operates at low voltages with excellent signal integrity and driving capability. To evaluate the performance of the new full adder in a real circuit, we embedded it in a 4- and 8-b, 4-operand carry-save array adder with final carry-propagate adder. The new adder displayed better performance as compared to the standard full adders

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Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style

This paper presents several architectures and designs of low-power 4-2 and 5-2 compressors capable of operating at ultra low supply voltages. These compressor architectures are anatomized into their constituent modules and different static logic styles based on the same deep submicrometer CMOS process model are used to realize them. Different configurations of each architecture, which include a number of novel 4-2 and 5-2 compressor designs, are prototyped and simulated to evaluate their performance in speed, power dissipation and power-delay product. The newly developed circuits are based on various configurations of the novel 5-2 compressor architecture with the new carry generator circuit, or existing architectures configured with the proposed circuit for the exclusive OR (XOR) and exclusive NOR ( XNOR) [XOR-XNOR] module. The proposed new circuit for the XOR-XNOR module eliminates the weak logic on the internal nodes of pass transistors with a pair of feedback PMOS-NMOS transistors. Driving capability has been considered in the design as well as in the simulation setup so that these 4-2 and 5-2 compressor cells can operate reliably in any tree structured parallel multiplier at very low supply voltages. Two new simulation environments are created to ensure that the performances reflect the realistic circuit operation in the system to which these cells are integrated. Simulation results show that the 4-2 compressor with the proposed XOR-XNOR module and the new fast 5-2 compressor architecture are able to function at supply voltage as low as 0.6 V, and outperform many other architectures including the classical CMOS logic compressors and variants of compressors constructed with various combinations of recently reported superior low-power logic cells.

/pdf/ultra-low-voltage-low-power-cmos-4-2-and-5-2-compressors-for-482wl2l598.pdf

Ultra low-voltage low-power CMOS 4-2 and 5-2 compressors for fast arithmetic circuits

The general objective of our work is to investigate the area and power-delay performances of low-voltage full adder cells in different CMOS logic styles for the predominating tree structured arithmetic circuits. A new hybrid style full adder circuit is also presented. The sum and carry generation circuits of the proposed full adder are designed with hybrid logic styles. To operate at ultra-low supply voltage, the pass logic circuit that cogenerates the intermediate XOR and XNOR outputs has been improved to overcome the switching delay problem. As full adders are frequently employed in a tree structured configuration for high-performance arithmetic circuits, a cascaded simulation structure is introduced to evaluate the full adders in a realistic application environment. A systematic and elegant procedure to scale the transistor for minimal power-delay product is proposed. The circuits being studied are optimized for energy efficiency at 0.18-/spl mu/m CMOS process technology. With the proposed simulation environment, it is shown that some survival cells in stand alone operation at low voltage may fail when cascaded in a larger circuit, either due to the lack of drivability or unsatisfactory speed of operation. The proposed hybrid full adder exhibits not only the full swing logic and balanced outputs but also strong output drivability. The increase in the transistor count of its complementary CMOS output stage is compensated by its area efficient layout. Therefore, it remains one of the best contenders for designing large tree structured arithmetic circuits with reduced energy consumption while keeping the increase in area to a minimum.

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A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits

Full adders are important components in applications such as digital signal processors (DSP) architectures and microprocessors. In this paper, we propose a technique to build a total of 41 new 10-transistor full adders using novel XOR and XNOR gates in combination with existing ones. We have done over 10,000 HSPICE simulation runs of all the different adders in different input patterns, frequencies, and load capacitances. Almost all those new adders consume less power in high frequencies, while three new adders consistently consume on average 10% less power and have higher speed compared with the previous 10-transistor full adder and the conventional 28-transistor CMOS adder. One draw back of the new adders is the threshold-voltage loss of the pass transistors.

Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates

The 1-bit full adder circuit is a very important component in the design of application specific integrated circuits. This paper presents a novel low-power multiplexer-based 1-bit full adder that uses 12 transistors (MBA-12T). In addition to reduced transition activity and charge recycling capability, this circuit has no direct connections to the power-supply nodes, leading to a noticeable reduction in short-current power consumption. Intensive HSPICE simulation shows that the new adder has more than 26% in power savings over conventional 28-transistor CMOS adder and it consumes 23% less power than 10-transistor adders (SERF and 10T ) and is 64% faster.

A novel multiplexer-based low-power full adder

Based on an algorithm derived from the new Chinese remainder theorem I, we present three new residue-to-binary converters for the residue number system (2/sup n/-1, 2/sup n/, 2/sup n/+1) designed using 2n-bit or n-bit adders with improvements on speed, area, or dynamic range compared with various previous converters. The 2n-bit adder based converter is faster and requires about half the hardware required by previous methods. For n-bit adder-based implementations, one new converter is twice as fast as the previous method using a similar amount of hardware, whereas another new converter achieves improvement in either speed, area, or dynamic range compared with previous converters.

/pdf/adder-based-residue-to-binary-number-converters-for-2-sup-n-4e975fpuo7.pdf

Adder based residue to binary number converters for (2/sup n/-1, 2/sup n/, 2/sup n/+1)

The speed of arithmetic operations depends on the size of the numbers involved. Smaller numbers have faster operations. That is exactly the reason why residue number systems are attractive in computer arithmetic. However, the conversion from residue to binary numbers involves a large number module operations. Several residue-to-binary converters are proposed in this paper. The converters are based on the New Chinese Remainder Theorems (CRT's) I and II which represent our work. The New CRT's improve the celebrated CRT. The new algorithms do not use any large size module adders. The numbers involved are much smaller compared to the numbers in the CRT and its alternative, the Mixed Radix Conversion method. Given a moduli set as (P/sub 1/, P/sub 2/,, P/sub n/), to convert a residue number (x/sub 1/,x/sub 2/,...,x/sub n/) to its decimal correspondence, a matrix of numbers bounded by P/sub i/ is needed for the New CRT I compared to the large numbers M/P/sub i/ for the CRT, where M=P/sub 1/P/sub 2/...P/sub n/. The New CRT II uses module multipliers of size less than /spl radic/M. If the condition P/sub i+1/>P/sub 1/+P/sub 2/+...+P/sub i/ is satisfied, only one module operation of size P/sub n/ is needed for the conversion. Residue-to-binary conversion based on the New CRT's presented here will have a significant impact on many algorithms which currently use the CRT, particularly in computer arithmetic such as residue number systems.

Residue-to-binary converters based on new Chinese remainder theorems

In this paper, a detailed study on the four three-moduli sets reported in the literature is carried out from the point of view of the hardware complexity and speed of their residue-to-binary (R/B) converters. First, a new formulation of the Chinese remainder theorem is proposed that reduces the size of the modulo operation. Then, the proposed formulation is applied to derive, in a simple and unified manner, R/B conversion algorithms for three of the sets. Further, using this formulation, a new algorithm along with two corresponding R/B converters for the fourth set is proposed; one of these converters is area efficient while the other is speed efficient. Next, the best R/B converter(s) for each of the sets is chosen based on the hardware complexity and/or speed. These converters are implemented for 8, 16, 32, and 64-bit dynamic ranges, using CMOS VLSI technology. Based on a post-layout performance evaluation for the VLSI implementations of the chosen converters, it is shown that in order to represent 8-, 16-, 32-, and 64-bit binary numbers, the moduli set {2/sup n/,2/sup n/+1,2/sup n/-1} provides the fastest R/B converter and requires the smallest area.

Yuke Wang

Papers

Design and analysis of low-power 10-transistor full adders using novel XOR-XNOR gates

A novel multiplexer-based low-power full adder

Adder based residue to binary number converters for (2/sup n/-1, 2/sup n/, 2/sup n/+1)

Residue-to-binary converters based on new Chinese remainder theorems

A study of the residue-to-binary converters for the three-moduli sets