Atomic layer deposition (ALD) has recently become the method of choice for the semiconductor industry to conformally process extremely thin insulating layers (high-k oxides) onto large-area silicon substrates. ALD is also a key technology for the surface modification of complex nanostructured materials. After briefly introducing ALD, this Review will focus on the various aspects of nanomaterials and their processing by ALD, including nanopores, nanowires and -tubes, nanopatterning and nanolaminates as well as low-temperature ALD for organic nanostructures and biomaterials. Finally, selected examples will be given of device applications, illustrating recent innovative approaches of how ALD can be used in nanotechnology.

https://www-old.mpi-halle.mpg.de/mpi/publi/pdf/7999_07.pdf

Synthesis and Surface Engineering of Complex Nanostructures by Atomic Layer Deposition

Semiconductor nanowires (NWs) have been studied extensively for over two decades for their novel electronic, photonic, thermal, electrochemical and mechanical properties. This comprehensive review article summarizes major advances in the synthesis, characterization, and application of these materials in the past decade. Developments in the understanding of the fundamental principles of "bottom-up" growth mechanisms are presented, with an emphasis on rational control of the morphology, stoichiometry, and crystal structure of the materials. This is followed by a discussion of the application of nanowires in i) electronic, ii) sensor, iii) photonic, iv) thermoelectric, v) photovoltaic, vi) photoelectrochemical, vii) battery, viii) mechanical, and ix) biological applications. Throughout the discussion, a detailed explanation of the unique properties associated with the one-dimensional nanowire geometry will be presented, and the benefits of these properties for the various applications will be highlighted. The review concludes with a brief perspective on future research directions, and remaining barriers which must be overcome for the successful commercial application of these technologies.

/pdf/25th-anniversary-article-semiconductor-nanowires-synthesis-4ccslz11ke.pdf

25th Anniversary Article: Semiconductor Nanowires – Synthesis, Characterization, and Applications

Memory effects are ubiquitous in nature and are particularly relevant at the nanoscale where the dynamical properties of electrons and ions strongly depend on the history of the system, at least within certain time scales. We review here the memory properties of various materials and systems which appear most strikingly in their non-trivial, time-dependent resistive, capacitative and inductive characteristics. We describe these characteristics within the framework of memristors, memcapacitors and meminductors, namely memory-circuit elements with properties that depend on the history and state of the system. We examine basic issues related to such systems and critically report on both theoretical and experimental progress in understanding their functionalities. We also discuss possible applications of memory effects in various areas of science and technology ranging from digital to analog electronics, biologically inspired circuits and learning. We finally discuss future research opportunities in the field.

Memory effects in complex materials and nanoscale systems

A review on various electrochemical techniques for heavy metal ions detection with different sensing platforms

This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Considerations for Ultimate CMOS Scaling

Effect of ambient gas on grain growth of CZTS layer: study on device efficiency

The paper reports a novel dual metal gate (MG) integration technique for gate-first CMOS process by intermixing (InM) of ultra-thin metal and metal nitride (MNx) films at high temperature together with source/drain (S/D) activation process. In this process, a thin (~2 nm) TaN buffer layer is used to prevent the gate dielectric being exposed during the metal etching process. Work function (WF) of TaN can be adjusted for NMOS/PMOS by intermixing of the TaN buffer layer with other metals on top of TaN during S/D activation. Prototype metal stacks of TaN/Tb/TaN (NMOS) and TaN/Ti/HfN (PMOS) have been integrated on a single wafer, with WF of 4.15 eV and 4.72 eV achieved, respectively. Successful Vth adjustment and good transistor characteristics are also demonstrated on HfTaON dielectric

CMOS Compatible Dual Metal Gate Integration with Successful Vth Adjustment on High-k HfTaON by High-Temperature Metal Intermixing

Novel Single and Dual Necking techniques S. Balakumar1, M. M. Roy, Ramamurthy, Gao Fei, Chih-Hang, R. kumar, N. Balasubramanian, S.Tripathy, S.J.Lee, and D.L. Kwong Institute of Microelectronics, 11 Science Park Road, Science Park 11, Singapore 117685 2 Department of Electrical and Computer Engineering National University of Singapore, 10, Singapore, 117576 Institute of Materials Research Engineering, 3 Research Link, Singapore, 117602, *Phone: +65-67705922, E-mail: subra@ime.a-star.edu.sg

Growth and Characterization of Germanium on Insulator (GOI) from Sputtered Ge by Novel Single and Dual Necking techniques

White mould caused by the fungal pathogen Sclerotinia sclerotiorum (Lib.) de Bary is one of the most important biological constraints to dry bean (Phaseolus vulgaris L.) production in Canada. Disease forecasting is one tool that could help growers manage the disease while reducing fungicide use. However, predicting white mould epidemics has remained difficult due to their sporadic occurrence. In this study, over the course of four growing seasons (2018 to 2021), we surveyed dry bean fields in Alberta and collected daily in-field weather data and daily in-field ascospore counts. White mould levels were variable and generally high in all years, confirming that the disease is ubiquitous and a constant threat to dry bean production. Ascospores were present throughout the growing season and mean ascospore levels varied by field, month, and year. Models based on in-field weather and ascospore levels were not highly predictive of final disease incidence in a field, suggesting that environment and pathogen presence were not limiting factors to disease development. Rather, significant effects of market class on disease were found, with pinto beans, on average, having the highest disease incidence (33%) followed by great northern (15%), black (10%), red (6%), and yellow (5%). When incidence of these market classes was modeled separately, different environmental variables were important in each model; however, average wind speed was a significant variable in all models. Taken together, these findings suggest that white mould management in dry bean should focus on fungicide use, plant genetics, irrigation management, and other agronomic factors.

N. Balasubramanian

Papers

Effect of ambient gas on grain growth of CZTS layer: study on device efficiency

CMOS Compatible Dual Metal Gate Integration with Successful Vth Adjustment on High-k HfTaON by High-Temperature Metal Intermixing

Growth and Characterization of Germanium on Insulator (GOI) from Sputtered Ge by Novel Single and Dual Necking techniques

Occurrence of ascospores and white mould caused by Sclerotinia sclerotiorum in dry bean fields in Alberta, Canada.

Studies of physio-chemical changes of dielectric barrier discharge plasma treated aramid fibers