Atomic layer deposition (ALD) has recently become the method of choice for the semiconductor industry to conformally process extremely thin insulating layers (high-k oxides) onto large-area silicon substrates. ALD is also a key technology for the surface modification of complex nanostructured materials. After briefly introducing ALD, this Review will focus on the various aspects of nanomaterials and their processing by ALD, including nanopores, nanowires and -tubes, nanopatterning and nanolaminates as well as low-temperature ALD for organic nanostructures and biomaterials. Finally, selected examples will be given of device applications, illustrating recent innovative approaches of how ALD can be used in nanotechnology.

https://www-old.mpi-halle.mpg.de/mpi/publi/pdf/7999_07.pdf

Synthesis and Surface Engineering of Complex Nanostructures by Atomic Layer Deposition

Semiconductor nanowires (NWs) have been studied extensively for over two decades for their novel electronic, photonic, thermal, electrochemical and mechanical properties. This comprehensive review article summarizes major advances in the synthesis, characterization, and application of these materials in the past decade. Developments in the understanding of the fundamental principles of "bottom-up" growth mechanisms are presented, with an emphasis on rational control of the morphology, stoichiometry, and crystal structure of the materials. This is followed by a discussion of the application of nanowires in i) electronic, ii) sensor, iii) photonic, iv) thermoelectric, v) photovoltaic, vi) photoelectrochemical, vii) battery, viii) mechanical, and ix) biological applications. Throughout the discussion, a detailed explanation of the unique properties associated with the one-dimensional nanowire geometry will be presented, and the benefits of these properties for the various applications will be highlighted. The review concludes with a brief perspective on future research directions, and remaining barriers which must be overcome for the successful commercial application of these technologies.

/pdf/25th-anniversary-article-semiconductor-nanowires-synthesis-4ccslz11ke.pdf

25th Anniversary Article: Semiconductor Nanowires – Synthesis, Characterization, and Applications

Memory effects are ubiquitous in nature and are particularly relevant at the nanoscale where the dynamical properties of electrons and ions strongly depend on the history of the system, at least within certain time scales. We review here the memory properties of various materials and systems which appear most strikingly in their non-trivial, time-dependent resistive, capacitative and inductive characteristics. We describe these characteristics within the framework of memristors, memcapacitors and meminductors, namely memory-circuit elements with properties that depend on the history and state of the system. We examine basic issues related to such systems and critically report on both theoretical and experimental progress in understanding their functionalities. We also discuss possible applications of memory effects in various areas of science and technology ranging from digital to analog electronics, biologically inspired circuits and learning. We finally discuss future research opportunities in the field.

Memory effects in complex materials and nanoscale systems

A review on various electrochemical techniques for heavy metal ions detection with different sensing platforms

This review paper explores considerations for ultimate CMOS transistor scaling Transistor architectures such as extremely thin silicon-on-insulator and FinFET (and related architectures such as TriGate, Omega-FET, Pi-Gate), as well as nanowire device architectures, are compared and contrasted Key technology challenges (such as advanced gate stacks, mobility, resistance, and capacitance) shared by all of the architectures will be discussed in relation to recent research results

Considerations for Ultimate CMOS Scaling

This paper presents a novel technique for tuning the work function of metal gate electrodes. Laminated metal gate electrodes consisting of 1/spl sim/3 ultra thin (/spl sim/10 /spl Aring/) layers of Ta, TaN, Ti, TiN, Hf or HfN and bulk metal nitride gate electrodes were deposited on SiO/sub 2/, HfO/sub 2/ or HfON, followed by RTP annealing to evaluate their thermal stability. Our results show that the work function of the laminated metal gate electrodes is significantly different from their bulk electrodes counterpart. Through lamination, a TiTaN/sub x/ alloy gate is formed which exhibits NMOS compatible work function (4.35 eV) with good thermal stability up to 900/spl deg/C. Laminated metal gates consisting of 3 components exhibit pMOS compatible work function (5,0/spl sim/5.2 eV) after 1000/spl deg/C annealing and this value remains unchanged after subsequent thermal processing. Possible mechanism responsible for work function tuning using laminated gates is discussed.

Laminated metal gate electrode with tunable work function for advanced CMOS

Trap layer engineered gate-all-around (GAA) silicon nanowire SONOS memory showing excellent device performance is demonstrated for the first time. Nitride and silicon nanocrystal (Si-NC) has have been incorporated as the engineered charge trapping layer. Fast transient memory characteristic is shown owing to the nanowire channel structure. The device with embedded Si-NC achieves even faster higher memory speed and increased window, up to 3.2 V DeltaVth shift for 1 mus and 6.25 V memory window. The nanowire based non-volatile SONOS memory is promising for the future high speed and low power NAND-type flash memory application.

Trap Layer Engineered Gate-All-Around Vertically Stacked Twin Si -Nanowire Nonvolatile Memory

A self-assembly method is demonstrated to link nanoparticles into nanostructure of nanochain or nanosphere. Gold nanoparticles were covered with capping molecules by forming Au–S bonds with thiol group at one terminate. Another terminating group, carboxylic acid, showed strong complex interaction with inorganic linker Zr4+ to form covalent complex bond. The different nanostructures were obtained by moving a balance between two opposite interactions, the linking interaction of Zr4+ and the electrostatic repulsive interaction of net surface charge. When the capping molecule with different chain length was used, the linked nanochain feature exhibited a tunable interdistance between the neighboring nanoparticles.

Preparation of nanochain and nanosphere by self-assembly of gold nanoparticles

High temperature oxidation and annealing are found to be desirable to achieve a uniform germanium (Ge) profile in silicon germanium on insulator (SGOI) layers formed using germanium condensation technique. This work investigates the amorphization mechanism, which was considered as an undesirable consequence of lowering the temperature during Ge condensation when oxidations are conducted at 900 or 950°C. A dual layer SGOI stack, composed of an amorphous layer above a crystalline layer, was obtained at low temperature condensation as characterized using transmission electron microscope and Auger analysis. A possible mechanism is presented. Si0.4Ge0.6OI and Si0.25Ge0.75OI layers can be achieved without amorphization through oxidation/annealing at 1050°C and two oxidations at 1050 and 1000°C, respectively.

SiGe amorphization during Ge condensation in silicon germanium on insulator

High performance Ge p- and n-MOSFETs with CVD HfO2 gate dielectric were fabricated Charge trapping and Vth instability were investigated systematically for the first time for Ge MOSFET with different surface treatments (silicon passivation and surface nitridation) and compared to the Si devices Our results show that: (1) Ge devices with silicon passivation yield better electrical performance and reliability than those with surface nitridation; (2) Ge transistors with silicon passivation exhibit less NBTI degradation than the silicon counterparts; probably due to the larger hole barrier in Ge/dielectric than in Si/dielectric; and (3) PBTI degradation of the Ge transistors is more severe than the silicon devices, which imposes an important reliability issue for Ge CMOS applications

N. Balasubramanian

Papers

Laminated metal gate electrode with tunable work function for advanced CMOS

Trap Layer Engineered Gate-All-Around Vertically Stacked Twin Si -Nanowire Nonvolatile Memory

Preparation of nanochain and nanosphere by self-assembly of gold nanoparticles

SiGe amorphization during Ge condensation in silicon germanium on insulator

BTI and charge trapping in germanium p- and n-MOSFETs with CVD HfO/sub 2/ gate dielectric