An array of memory cells configured to store at least one bit per one F 2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt 1 ) and a second voltage threshold region (Vt 2 ) and such that the programmed cell operates at reduced drain source current.

NROM memory cell, memory array, related devices and methods

Structures and methods for vertical memory cell. The vertical memory cell includes a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate. The MOSFET has a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator. A first transmission line is coupled to the first source/drain region. A second transmission line is coupled to the second source/drain region. The MOSFET is adapted to be programmed to have a charge trapped in at least one of a first storage region and a second storage region in the gate insulator and operated with either the first source/drain region or the second source/drain region serving as the source region.

Vertical NROM having a storage density of 1 bit per 1F2

A well-known effect in flash memories is stress-induced leakage in a small fraction of memory cells after program/erase cycling. This paper presents a comprehensive statistical reliability model with an excellent fit to data collected on several technology generations in multi-year bakes. The leakage current is exponential in voltage and has a low but nonzero activation energy. The statistical variation is Weibull. The fraction of cells affected scales as a power law in cycle count, with significant dependence on the vertical and horizontal electric fields in cycling but little on the cycling temperature. A single model equation comprehends all of these effects. The mechanism anneals or recovers at moderate temperatures in a manner sensitive to processing details, which are discussed. A new technique is introduced to deduce the number of traps involved in the trap-assisted-tunneling (percolation) paths by correlating the effect to oxide trap density using cycling-induced erase-time push-out. The results suggest that the percolation paths consist of only a small number of traps, most likely two. Contrary to predictions that this mechanism is a hard barrier to scaling of flash memory, we show that it has been possible to reduce the effect by several orders of magnitude over the course of several generations of technology scaling.

A new reliability model for post-cycling charge retention of flash memories

A significant improvement in device performance and reliability characteristics of silicon-oxide-nitride-oxide-silicon (SONOS) Flash memory has been achieved. Superior endurance characteristic shows no sign of degradation even after 10/sup 6/ program/erase cycles and an extrapolated ten-year detection window of 1.4 V has been attained from retention measurement. The dramatic improvement results from a bandgap engineering of the SiN charge-trapping layer. With a gradual variation of the Si/N ratio from bottom to top of nitride film rather than uniform standard composition, a large number of highly accessible trapping levels are created in addition to the deepened barrier height between nitride and tunnel oxide that reduces back-tunneling probability. The proposed technique shall be valuable in pushing Flash memory technology into the next generation.

Performance improvement of SONOS memory by bandgap engineering of charge-trapping layer

A high permittivity tunneling dielectric is used in a flash memory cell to provide greater tunneling current into the floating gate with smaller gate voltages The flash memory cell has a substrate with source/drain regions The high-k tunneling dielectric is formed above the substrate The high-k tunneling dielectric can be deposited using evaporation techniques or atomic layer deposition techniques The floating gate is formed on top of the high-k dielectric layer with an oxide gate insulator on top of that A polysilicon control gate is formed on the top gate insulator

Flash memory having a high-permittivity tunnel dielectric

Data retention loss in a localized trapping storage flash memory cell with a SONOS type structure is investigated. Both charge loss through the bottom oxide and lateral migration of trapped charges in the nitride layer are considered for the data retention loss. Charge pumping and charge separation methods are used in this study. Our results reveal that in normal operation condition the retention loss is mainly caused by charge leakage via P/E stress created oxide traps.

Cause of data retention loss in a nitride-based localized trapping storage flash memory cell

The RC-based power-rail ESD clamp circuit with the n-channel metal-oxide-semiconductor (NMOS) transistor drawn in the layout style of big field-effect transistor (BigFET) has been utilized to effectively enhance the ESD robustness of CMOS ICs. In this work, a new ESD-transient detection circuit without using the capacitor has been proposed and verified in a 65 nm 1.2 V CMOS process. The layout area of the new ESD-transient detection circuit can be greatly reduced by more than 54%, as compared to the traditional RC-based ESD-transient detection circuit realized with capacitor. From the experimental results, the new proposed ESD-transient detection circuit with adjustable holding voltage can achieve long enough turn-on duration under the ESD stress condition, as well as better immunity against mistrigger and transient-induced latch-on event under the fast power-on and transient noise conditions.

https://ir.nctu.edu.tw:443/bitstream/11536/32011/1/000283442500026.pdf

Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection

The diode operated in forward-biased condition has been widely used as an effective on-chip electrostatic discharge (ESD) protection device at radio-frequency (RF) front-end and high-speed input/output (I/O) pads due to the small parasitic loading effect and high ESD robustness in CMOS integrated circuits (ICs). This work presents new ESD protection diodes drawn in the octagon, waffle-hollow, and octagon-hollow layout styles to improve the efficiency of ESD current distribution and to reduce the parasitic capacitance. The measured results confirmed that they can achieve smaller parasitic capacitance under the same ESD robustness level as compared to the stripe and waffle diodes, especially for the diodes drawn in the hollow layout style. Therefore, the signal degradation of RF and high-speed transmission can be reduced because of smaller parasitic capacitance from the new proposed diodes.

/pdf/optimization-on-layout-style-of-esd-protection-diode-for-26s57jhd6p.pdf

Optimization on Layout Style of ESD Protection Diode for Radio-Frequency Front-End and High-Speed I/O Interface Circuits

A power-rail electrostatic discharge (ESD) clamp circuit realized with ESD clamp device drawn in the layout style of big field-effect transistor (BigFET), and with parasitic diode of BigFET as a part of ESD-transient detection mechanism, is proposed and verified in a 65-nm 1.2-V CMOS process. Skillfully utilizing the diode-connected MOS transistor as the equivalent large resistor and the parasitic reverse-biased diodes of BigFET as the equivalent capacitors, the new RC-based ESD-transient detection mechanism can be achieved without using an actual resistor and capacitor to significantly reduce the layout area by ~82%, as compared to the traditional RC-based ESD-transient detection circuit. From the measured results, the new proposed power-rail ESD clamp circuit with body effect of ESD clamp device can perform adjustable holding voltage under the ESD stress condition, as well as better immunity against mistrigger and transient-induced latch-on under fast power-on and transient noise conditions.

https://ir.nctu.edu.tw:443/bitstream/11536/21747/1/000316820000016.pdf

High Area-Efficient ESD Clamp Circuit With Equivalent $RC$ -Based Detection Mechanism in a 65-nm CMOS Process

A new power-rail ESD clamp circuit designed with PMOS as main ESD clamp device has been proposed and verified in a 65nm 1.2V CMOS process. The new proposed design with adjustable holding voltage controlled by the ESD detection circuit has better immunity against mis-trigger or transient-induced latch-on event. The layout area and the standby leakage current of this new proposed design are much superior to that of traditional RC-based power-rail ESD clamp circuit with NMOS as main ESD clamp device.

/pdf/pmos-based-power-rail-esd-clamp-circuit-with-adjustable-q2685svi95.pdf

Chih-Ting Yeh

Papers

Cause of data retention loss in a nitride-based localized trapping storage flash memory cell

Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection

Optimization on Layout Style of ESD Protection Diode for Radio-Frequency Front-End and High-Speed I/O Interface Circuits

High Area-Efficient ESD Clamp Circuit With Equivalent $RC$ -Based Detection Mechanism in a 65-nm CMOS Process

PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit