Amorphous InGaZnOx (a-IGZO) thin-film transistors (TFTs) are currently used in flat-panel displays due to their beneficial properties. However, the mobility of ∼10 cm2/(V s) for the a-IGZO TFTs used in commercial organic light-emitting diode TVs is not satisfactory for high-resolution display applications such as virtual and augmented reality applications. In general, the electrical properties of amorphous oxide semiconductors are strongly dependent on their chemical composition; the indium (In)-rich IGZO achieves a high mobility of 50 cm2/(V s). However, the In-rich IGZO TFTs possess another issue of negative threshold voltage owing to intrinsically high carrier density. Therefore, the development of an effective way of carrier density suppression in In-rich IGZO will be a key strategy to the realization of practical high-mobility a-IGZO TFTs. In this study, we report that In-rich IGZO TFTs with vertically stacked InOx, ZnOx, and GaOx atomic layers exhibit excellent performances such as saturation mobilities of ∼74 cm2/(V s), threshold voltage of -1.3 V, on/off ratio of 8.9 × 108, subthreshold swing of 0.26 V/decade, and hysteresis of 0.2 V, while keeping a reasonable carrier density of ∼1017 cm-3. We found that the vertical dimension control of IGZO active layers is critical to TFT performance parameters such as mobility and threshold voltage. This study illustrates the potential advantages of atomic layer deposition processes for fabricating ultrahigh-mobility oxide TFTs.

Amorphous IGZO TFT with High Mobility of ∼70 cm2/(V s) via Vertical Dimension Control Using PEALD

Since the introduction of a 3-D NAND product in 2014, the areal density has increased by more than 8 times (from 0.96 to 7.80 Gb/mm2) in the recent five years. The increase of word-line (WL) stacking from 24 to 128 layers, the scaling of bits per cell from 2 to 3 bits/cell and 4 bits/cell, and a CMOS under array technology enabled this successful 3-D NAND density scaling. A gate-all-around cell architecture realized excellent reliability and program/read performance by having a large physical cell size and good shielding of cell-to-cell interference. In the newly introduced 3-D NAND devices, several new cell phenomena have been reported. Unique temperature dependence and threshold-voltage instability are observed due to the polysilicon channel. Down-coupling of the floating body and its impact on program disturb and hot electron injection were reported. The cell-to-cell interference is enhanced by the effective gate length modulation due to the no-lightly doped drain (LDD) string architecture. For the future 3-D NAND scaling, WL stacking will continue to be a key driver. In addition, XYZ dimension shrink of the cell will become another key critical scaling direction in order to relieve the cost and device challenges introduced by the WL stacking. Various device and structure solutions for the XYZ cell scaling have been suggested. The good engineering in number of electrons and cell-to-cell interference in the XYZ scaled cell will be critical in order to maintain the excellent reliability and performance of 3-D NAND.

3-D NAND Technology Achievements and Future Scaling Perspectives

We review the state-of-the-art in the understanding of planar NAND Flash memory reliability and discuss how the recent move to three-dimensional (3D) devices has affected this field. Particular emphasis is placed on mechanisms developing along the lifetime of the memory array, as opposed to time-zero or technological issues, and the viewpoint is focused on the understanding of the root causes. The impressive amount of published work demonstrates that Flash reliability is a complex yet well-understood field, where nonetheless tighter and tighter constraints are set by device scaling. Three-dimensional NAND have offset the traditional scaling scenario, leading to an improvement in performance and reliability while raising new issues to be dealt with, determined by the newer and more complex cell and array architectures as well as operation modes. A thorough understanding of the complex phenomena involved in the operation and reliability of NAND cells remains vital for the development of future technology nodes.

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Reliability of NAND Flash Memories: Planar Cells and Emerging Issues in 3D Devices

This paper reviews what changed in the reliability of NAND Flash memory arrays after the paradigm shift in technology evolution determined by the transition from 2-D to 3-D integration schemes. Starting from a quick glance at the fundamentals of raw array reliability, the reasons for its worsening with the evolution of 2-D technologies will be discussed, focusing on the physical phenomena which contributed more to that outcome. By exploring the dependence of the magnitude of these phenomena on cell and array parameters, the abrupt improvements achieved from the 3-D transition in terms of raw array reliability will then be explained, highlighting also that these improvements were turned into new opportunities for the technology. Finally, the physical issues specific to 3-D arrays will be addressed, providing a glimpse of the challenges that the NAND Flash technology will have to face from the standpoint of array reliability in the near future.

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Reliability of NAND Flash Arrays: A Review of What the 2-D–to–3-D Transition Meant

A novel operation scheme is proposed for high-density and highly robust neuromorphic computing based on NAND flash memory architecture. Analog input is represented with time-encoded input pulse by pulse width modulation (PWM) circuit, and 4-bit synaptic weight is represented with adjustable conductance of NAND cells. Pulse width modulation scheme for analog input value and proposed operation scheme is suitably applicable to the conventional NAND flash architecture to implement a neuromorphic system without additional change of memory architecture. Saturated current-voltage characteristic of NAND cells eliminates the effect of serial resistance of adjacent cells where a pass bias is applied in a synaptic string and IR drop of metal wire resistance. Multiply-accumulate (MAC) operation of 4-bit weight and width-modulated input can be performed in a single input step without additional logic operation. Furthermore, the effect of quantization training (QT) on the classification accuracy is investigated compared with post-training quantization (PTQ) with 4-bit weight. Lastly, a sufficiently low current variance of NAND cells obtained by the read-verify-write (RVW) scheme achieves satisfying accuracies of 98.14 and 89.6% for the MNIST and CIFAR10 images, respectively.

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Neuromorphic Computing Using NAND Flash Memory Architecture With Pulse Width Modulation Scheme.

Retention characteristics of a 3-D NAND flash cell with tube-type poly-Si body are investigated at a high temperature (T) depending on program (P), neutral (N), and erase (E) states of adjacent cells. The trap density (N t ) in the nitride storage layer of the cell is extracted by utilizing retention model and deriving related equations in cylindrical coordinate. By programming or erasing adjacent cells, we can separate laterally distributed charge component from the retention characteristics. The adjacent cells which are programmed suppress significantly the lateral diffusion at a high T so that we can extract accurate N t profile. Extracted peak of N t at P-P-P mode is ∼1.2×1019 cm−3eV−1 at an E C -E T of 1.0 eV. Retention characteristics with effective gate length and word-line biasing are also investigated.

Comprehensive analysis of retention characteristics in 3-D NAND flash memory cells with tube-type poly-Si channel structure

Four synaptic devices are introduced for spiking neural networks (SNNs) and deep neural networks (DNNs). Unsupervised learning is successfully demonstrated by applying the STDP learning rule reflecting the LTP/LTD characteristics of the fabricated TFT-type NOR flash memory cells. Gated Schottky diode (GSD) and vertical NAND flash cell are proposed as synaptic device for DNNs. Using matched simulation, we obtained higher learning accuracy with GSD and NAND synaptic devices compared to that with a memristor-based synapse. Measured synaptic properties of the vertical NAND cells are reported for the first time.

Neuromorphic Technology Based on Charge Storage Memory Devices

A positive feedback (PF) mechanism was adopted for the first time in the cell string of a 3-D NAND flash memory where n + and p + regions are formed on both ends of the string to implement a diode-type cell string. The body consists of a tube-type poly-Si channel. To generate the PF in the channel during a read operation, a new read operation scheme is proposed. In this paper, the simulator was calibrated in terms of trap density ( $D_{\mathrm {it}})$ of a poly-Si channel extracted from fabricated 3-D NAND flash memory cells. By utilizing the PF, a NAND flash memory cell in a cell string has a steep subthreshold swing of <1 mV/decade.

Diode-Type NAND Flash Memory Cell String Having Super-Steep Switching Slope Based on Positive Feedback

A new space program (PGM) scheme is proposed to achieve reliable triple-level-cell (TLC) 3-D NAND flash memory. Considering the lateral diffusion issue of stored electrons in the nitride storage layer, the proposed scheme stores electrons in the nitride layer of the space region between adjacent cells to suppress the lateral movement of trapped electrons in the programmed target cells. The effect of the space PGM can be sustained until 104 s at 90 °C and up to 1k read cycles at 25 °C. The programmed space region of the nitride layer improves the retention characteristics of the cells in the PGM state by 40% and remarkably reduces the V th redistribution.

Space Program Scheme for 3-D NAND Flash Memory Specialized for the TLC Design

A positive-feedback (PF) neuron device capable of threshold tuning and simultaneously processing excitatory ( $G^{+}$ ) and inhibitory ( $G^{-}$ ) signals is experimentally demonstrated to replace conventional neuron circuits, for the first time. Thanks to the PF operation, the PF neuron device with steep switching characteristics can implement integrate-and-fire (IF) function of neurons with low-energy consumption. The structure of the PF neuron device efficiently merges a gated PNPN diode and a single MOSFET. Integrate-and-fire (IF) operation with steep subthreshold swing ( SS $n$ floating body of the PF neuron device. The carriers accumulated in the $n$ floating body are discharged by an inhibitory signal applied to the merged FET. Moreover, the threshold voltage ( $V_{\mathrm {th}}$ ) of the proposed PF neuron is controlled by using a charge storage layer. The low-energy consuming PF neuron circuit (~0.62 pJ/spike) consists of one PF device and only five MOSFETs for the IF and reset operation. In a high-level system simulation, a deep-spiking neural network (D-SNN) based on PF neurons with four hidden layers (1024 neurons in each layer) shows high-accuracy (98.55%) during a MNIST classification task. The PF neuron device provides a viable solution for high-density and low-energy neuromorphic systems.

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Nagyong Choi

Papers

Comprehensive analysis of retention characteristics in 3-D NAND flash memory cells with tube-type poly-Si channel structure

Neuromorphic Technology Based on Charge Storage Memory Devices

Diode-Type NAND Flash Memory Cell String Having Super-Steep Switching Slope Based on Positive Feedback

Space Program Scheme for 3-D NAND Flash Memory Specialized for the TLC Design

Low-Power and High-Density Neuron Device for Simultaneous Processing of Excitatory and Inhibitory Signals in Neuromorphic Systems