Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389

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Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications

High-k/Ge MOSFETs for future nanoelectronics

ldquoConventionalrdquo techniques and related capacitance-voltage characteristic interpretation were established to evaluate interface trap density on Si substrates. We show that blindly applying these techniques on alternative substrates can lead to incorrect conclusions. It is possible to both under- and overestimate the interface trap density by more than an order of magnitude. Pitfalls jeopardizing capacitance-and conductance-voltage characteristic interpretation for alternative semiconductor MOS are elaborated. We show how the conductance method, the most reliable and widely used interface trap density extraction method for Si, can be adapted and made reliable for alternative semiconductors while maintaining its simplicity.

On the Correct Extraction of Interface Trap Density of MOS Devices With High-Mobility Semiconductor Substrates

In this paper, electrical and interfacial properties of MOS capacitors with atomic layer deposited (ALD) Al2O3, HfO2, and HfAlO gate dielectrics on sulfur-passivated (S-passivated) GaAs substrates were investigated. HfAlO on p-type GaAs has shown superior electrical properties over Al2O3 or HfO2 on GaAs, and it is attributed to the reduction of the Ga-O formation at the interfacial layer. HfAlO on p-type GaAs exhibits the best electrical properties after postdeposition annealing (PDA) at 500degC. It is found that PDA, at above 500degC, causes a significant amount of Ga and As out-diffusion into the high-k dielectric, which degrades the interface, as well as bulk high-k properties.

Electrical and Interfacial Characterization of Atomic Layer Deposited High- $\kappa$ Gate Dielectrics on GaAs for Advanced CMOS Devices

Due to its high intrinsic mobility, germanium (Ge) is a promising candidate as a channel material (offering a mobility gain of approximately??2 for electrons and??4 for holes when compared to conventional Si channels) However, many issues still need to be addressed before Ge can be implemented in high-performance field-effect-transistor (FET) devices One of the key issues is to provide a high-quality interfacial layer, which does not lead to substantial drive current degradation in both low equivalent oxide thickness and short channel regime In recent years, a wide range of materials and processes have been investigated to obtain proper interfacial properties, including different methods for Ge surface passivation, various high-k dielectrics and metal gate materials and deposition methods, and different post-deposition annealing treatments It is observed that each process step can significantly affect the overall metal?oxide?semiconductor (MOS)-FET device performance In this review, we describe and compare combinations of the most commonly used Ge surface passivation methods (eg epi-Si passivation, surface oxidation and/or nitridation, and S-passivation) with various high-k dielectrics In particular, plasma-based processes for surface passivation in combination with plasma-enhanced atomic layer deposition for high-k depositions are shown to result in high-quality MOS structures To further improve properties, the gate stack can be annealed after deposition The effects of annealing temperature and ambient on the electrical properties of the MOS structure are also discussed

https://iopscience.iop.org/article/10.1088/0268-1242/27/7/074012/pdf

Germanium surface passivation and atomic layer deposition of high-k dielectrics—a tutorial review on Ge-based MOS capacitors

In this paper, silicon (Si) nanocrystal memory using chemical vapor deposition (CVD) HfO/sub 2/ high-k dielectrics to replace the traditional SiO/sub 2/ tunneling/control dielectrics has been fabricated and characterized for the first time. The advantages of this approach for improved nanocrystal memory operation have also been studied theoretically. Results show that due to its unique band asymmetry in programming and retention mode, the use of high-k dielectric on Si offers lower electron barrier height at dielectric/Si interface and larger physical thickness, resulting in a much higher J/sub g,programming//J/sub g,retention/ ratio than that in SiO/sub 2/ and therefore faster programming and longer retention. The fabricated device with CVD HfO/sub 2/ shows excellent programming efficiency and data-retention characteristics, thanks to the combination of a lower electron barrier height and a larger physical thickness of HfO/sub 2/ as compared with SiO/sub 2/ of the same electrical oxide thickness (EOT). It also shows clear single-electron charging effect at room temperature and superior data endurance up to 10/sup 6/ write/erase cycles.

Theoretical and experimental investigation of Si nanocrystal memory device with HfO/sub 2/ high-k tunneling dielectric

MOS devices built on various germanium substrates, with chemical vapor deposited (CVD) or physical vapor deposited (PVD) HfO2 high-kappa dielectric and TaN gate electrode, were fabricated. The electrical properties of these devices, including the capacitance equivalent thickness (CET), gate leakage current density (Jg), slow trap density (Dst), breakdown voltage (Vbd), capacitance-voltage (C-V) frequency dispersion, and thermal stability, are investigated. The process conditions such as surface nitridation treatment, O2 introduction in CVD process and postdeposition anneal temperature in PVD process, exhibit significant impacts on the devices' electrical properties. The devices built on germanium substrates with different dopant types and doping concentrations show remarkable variations in electrical characteristics, revealing the role of the substrate doping in the reactions occurring at the dielectric/Ge interface, which can significantly affect the interfacial layer formation and Ge updiffusion. A possible mechanism is suggested that two competing processes (oxide growth and desorption) take place at the interface, which govern the formation of the interfacial layer. Doped p-type (Ga) and n-type (Sb) impurities may enhance the different process at the interface and cause the variations in the interfacial layer formation and so on in electrical properties. The high diffusivities of impurities and Ge atoms in Ge and the induced structural defects near the substrate surface could be one possible cause for this doping effect. As another behavior of the substrate doping effect, Ge n-MOS and p-MOS stacks show quite different C-V characteristics after high temperature postmetallization anneal treatments, which can be explained by the same mechanism

The electrical properties of HfO/sub 2/ dielectric on germanium and the substrate doping effect

The authors investigated the optical and electrical properties of the high permittivity (κ) metal oxides, HfTiO and HfTaTiO, using HfO2 as a reference and compared their material properties against their electrical performance. HfTiO has a higher κ value but its band offset is relatively smaller and, therefore, it has greater gate leakage current than HfO2. HfTaTiO has an even higher κ value which compensates for the impact of its small band offset. In addition, HfO2 was found to have more defect states than the other two films, which caused a larger hysteresis in the capacitance-voltage scan and degraded channel mobility.

High permittivity quaternary metal (HfTaTiOx) oxide layer as an alternative high-κ gate dielectric

An in situ surface-cleaning technique by annealing germanium substrates at 550 degC in Ar gas is investigated. Reduced equivalent oxide thickness confirms the effective removal of native oxides by this technique. Improved electrical characteristics in terms of reduced interface-state density and slow trap density are demonstrated in the Ge MOS devices, with surface-nitridation treatment and chemical vapor deposited HfO2 high-kappa dielectric, suggesting the advantage of this technique. Significant elimination of GeOxN y interfacial layer is observed from cross-sectional transmission electron microscopy images after 600 degC postmetallization anneal, suggesting that an interface passivation technique having better thermal stability is required in order to suppress the severe interdiffusion across the interface between Ge substrate and the upper dielectric layer

Nan Lu

Papers

Theoretical and experimental investigation of Si nanocrystal memory device with HfO/sub 2/ high-k tunneling dielectric

The electrical properties of HfO/sub 2/ dielectric on germanium and the substrate doping effect

High permittivity quaternary metal (HfTaTiOx) oxide layer as an alternative high-κ gate dielectric

In situ cleaning effect on the electrical properties of Ge MOS devices by Ar gas anneal