Embodiments related to managing the process feed conditions for a semiconductor process module are provided. In one example, a gas channel plate for a semiconductor process module is provided. The example gas channel plate includes a heat exchange surface including a plurality of heat exchange structures separated from one another by intervening gaps. The example gas channel plate also includes a heat exchange fluid director plate support surface for supporting a heat exchange fluid director plate above the plurality of heat exchange structures so that at least a portion of the plurality of heat exchange structures are spaced from the heat exchange fluid director plate.

Process feed management for semiconductor substrate processing

A method for making a semiconductor device is described. That method comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer. The oxide layer and the high-k dielectric layer are then annealed at a sufficient temperature for a sufficient time to generate a gate dielectric with a graded dielectric constant.

Method for making a semiconductor device having a high-k gate dielectric

The present invention relates to a process and system for depositing a thin film onto a substrate. One aspect of the invention is depositing a thin film metal oxide layer using atomic layer deposition (ALD).

Systems and methods for thin-film deposition of metal oxides using excited nitrogen-oxygen species

A showerhead including a body having an opening, a first plate positioned within the opening and having a plurality of slots, a second plate positioned within the opening and having a plurality of slots, and wherein each of the first plate plurality of slots are concentrically aligned with the second plate plurality of slots.

Semiconductor reaction chamber showerhead

A reactor having a housing that encloses a gas delivery system operatively connected to a reaction chamber and an exhaust assembly. The gas delivery system includes a plurality of gas lines for providing at least one process gas to the reaction chamber. The gas delivery system further includes a mixer for receiving the at least one process gas. The mixer is operatively connected to a diffuser that is configured to diffuse process gases. The diffuser is attached directly to an upper surface of the reaction chamber, thereby forming a diffuser volume therebetween. The diffuser includes at least one distribution surface that is configured to provide a flow restriction to the process gases as they pass through the diffuser volume before being introduced into the reaction chamber.

Semiconductor processing reactor and components thereof

Metal-insulator-metal (MIM) capacitors with insulator stacks having a plurality of metal oxide layers are described. For example, a MIM capacitor for a semiconductor device includes a trench disposed in a dielectric layer disposed above a substrate. A first metal plate is disposed along the bottom and sidewalls of the trench. An insulator stack is disposed above and conformal with the first metal plate. The insulator stack includes a first metal oxide layer having a first dielectric constant and a second metal oxide layer having a second dielectric constant. The first dielectric constant is higher than the second dielectric constant. The MIM capacitor also includes a second metal plate disposed above and conformal with the insulator stack.

Metal-insulator-metal (mim) capacitor with insulator stack having a plurality of metal oxide layers

A method for making a semiconductor device is described. That method comprises forming on a substrate a buffer layer and a high-k gate dielectric layer, oxidizing the surface of the high-k gate dielectric layer, and then forming a gate electrode on the oxidized high-k gate dielectric layer.

A method for making a semiconductor device having an ultra-thin high-k gate dielectric

Semiconductor structures having integrated double-wall capacitors for eDRAM and methods to form the same are described For example, an embedded double-wall capacitor includes a trench disposed in a first dielectric layer disposed above a substrate The trench has a bottom and sidewalls A U-shaped metal plate is disposed at the bottom of the trench, spaced apart from the sidewalls A second dielectric layer is disposed on and conformal with the sidewalls of the trench and the U-shaped metal plate A top metal plate layer is disposed on and conformal with the second dielectric layer

Semiconductor structure having an integrated double-wall capacitor for embedded dynamic random access memory (edram) and method to form the same

Methods and architectures for self-aligned build-up of patterned features. An initial patterned feature aspect ratio may be maintained or increased, for example to mitigate erosion of the feature during one or more subtractive device fabrication processes. A patterned feature height may be increased without altering an effective spacing between adjacent features that may be further relied upon, for example to further pattern an underlying material. A patterned feature may be conformally capped with a material, such as a metal or dielectric, in a self-aligned manner, for example to form a functional device layer on an initial pattern having a suitable space width-to-line height aspect ratio without the use of a masked etch to define the cap.

Self-aligned build-up of topographic features

L'invention concerne un procede de fabrication d'un dispositif a semi-conducteur, qui consiste a former sur un substrat une couche tampon et une couche dielectrique de grille a constant k elevee, a oxyder la surface de la couche dielectrique de grille a constant k elevee, et a former une electrode de grille sur la couche dielectrique de grille a constante k elevee oxydee.

Nick Lindert

Papers

Metal-insulator-metal (mim) capacitor with insulator stack having a plurality of metal oxide layers

A method for making a semiconductor device having an ultra-thin high-k gate dielectric

Semiconductor structure having an integrated double-wall capacitor for embedded dynamic random access memory (edram) and method to form the same

Self-aligned build-up of topographic features

Procede de fabrication d'un dispositif a semi-conducteur ayant un dielectrique de grille a constante k elevee ultra-mince