M
Matthew V. Metz
Researcher at Intel
Publications - 133
Citations - 5933
Matthew V. Metz is an academic researcher from Intel. The author has contributed to research in topics: Gate dielectric & Gate oxide. The author has an hindex of 41, co-authored 129 publications receiving 5674 citations.
Papers
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Journal ArticleDOI
Benchmarking nanotechnology for high-performance and low-power logic transistor applications
R. Chau,Suman Datta,Mark Beaverton Doczy,B. Doyle,B. Jin,Jack Portland Kavalieros,Amlan Majumdar,Matthew V. Metz,Marko Radosavljevic +8 more
TL;DR: The results of this benchmarking exercise indicate that while these novel nanoelectronic devices show promise and opportunities for future logic applications, there still remain shortcomings in the device characteristics and electrostatics that need to be overcome.
Journal ArticleDOI
High-/spl kappa//metal-gate stack and its MOSFET characteristics
TL;DR: In this paper, the authors show that surface phonon scattering in the high/spl kappa/ dielectric is the primary cause of channel electron mobility degradation, and demonstrate that metal-gate electrodes, such as the ones with n+ and p+ work functions, are effective in improving channel mobilities to close to those of the conventional SiO/sub 2/poly-Si stack.
Proceedings ArticleDOI
Fabrication, characterization, and physics of III–V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing
G. Dewey,Benjamin Chu-Kung,J. Boardman,J. M. Fastenau,Jack Portland Kavalieros,Roza Kotlyar,W. K. Liu,D. Lubyshev,Matthew V. Metz,Niloy Mukherjee,P. Oakey,Ravi Pillarisetty,Marko Radosavljevic,Han Wui Then,R. Chau +14 more
TL;DR: In this paper, the steepest sub-threshold swing (SS < 60mV/decade) was achieved in a III-V TFET by using thin gate oxide, heterojunction engineering and high source doping.
Patent
Method for making a semiconductor device having a high-k gate dielectric
Mark L. Doczy,Gilbert Dewey,Suman Datta,Sangwoo Pae,Justin K. Brask,Jack T. Kavalieros,Matthew V. Metz,Adrian B. Sherrill,Markus Kuhn,Robert S. Chau +9 more
TL;DR: In this paper, a method for making a semiconductor device is described, which comprises forming an oxide layer on a substrate, and forming a high-k dielectric layer on the oxide layer.
Proceedings ArticleDOI
Tri-Gate Transistor Architecture with High-k Gate Dielectrics, Metal Gates and Strain Engineering
Jack Portland Kavalieros,B. Doyle,Suman Datta,G. Dewey,Mark Beaverton Doczy,B. Jin,D. Lionberger,Matthew V. Metz,Willy Rachmady,Marko Radosavljevic,Uday Shah,Nancy M. Zelick,R. Chau +12 more
TL;DR: In this paper, the benefits of the fully depleted tri-gate transistor architecture with high-k gate dielectrics, metal gate electrodes and strain engineering are combined with high performance NMOS and PMOS trigate transistors.