This paper describes a 28-Gb/s receiver IC with self-contained adaptive equalization and sampling point control using an on-chip stochastic sigma-tracking eye-opening monitor (SSEOM). The proposed SSEOM accurately detects the bit-error-rate (BER)-related eye contour efficiently without the use of an external microcontroller. The SSEOM determines the BER-optimal sampling point and equalizer coefficients on the basis of pattern-filtered eye diagrams. It also features a background adaptation scheme for robust long-term operation by tracking temperature variations and device aging. The proposed SSEOM is integrated in a 28-Gb/s receiver that is designed to compensate for channel loss up to 25 dB at the Nyquist rate by using a continuous time linear equalizer (CTLE) and a one-tap decision feedback equalizer (DFE) together with an one-tap pre-emphasis at a transmitter. The time required for complete adaptation and the total power consumption are 364 ms and 43.9 mW, respectively. The proposed 28-Gb/s receiver is fabricated in 40 nm CMOS.

A 28-Gb/s Receiver With Self-contained Adaptive Equalization and Sampling Point Control Using Stochastic Sigma-Tracking Eye-Opening Monitor

Pushed by the ever-increasing demand of internet traffic, high-speed serial interfaces are expected to reach 400-Gb/s aggregate data rates in near future. At receiver (RX) side, phase rotators (PRs) are key blocks to align the phase of the local clock to the transitions of the incoming data and to sample the eye in the optimal position. Small phase step and high linearity are paramount in preserving the horizontal time margin, tightened by the reduced symbol duration at 25 Gb/s and beyond. Interpolation of $\pi $ /4-spaced signals is a viable means of improving linearity at high resolution, provided multi-phase signals with low phase error are available. An injection-locked ring oscillator (ILRO) with a mixed analog and digital calibration loop is proposed for high accuracy multi-phase generation over a wide frequency range and against large voltage and temperature variations. A phase detector (PD) based on two passive mixers measures the quadrature error and continuously tunes the oscillator to achieve low phase error. Concurrently, a window comparator monitors the PD output and drives digital coarse calibration in background. Two test chips have been fabricated in 28-nm CMOS fully depleted silicon on insulator technology. The stand-alone ILRO demonstrates 0.2–11.7 GHz frequency range with better than 1.5° quadrature phase error over ±20% supply and −40 °C to +120 °C temperature variations. Power consumption is scalable from 3 to 15 mW. When the ILRO drives the 7-bit PR, it demonstrates differential and integral non-linearity within 0.5 and 1.1 LSB, respectively, across the 2–11 GHz frequency range with 18.6-mW maximum power dissipation. Measured performances compare favorably against the state of the art and meet the requirements of >25 Gb/s multi-standard I/O RXs.

A 2–11 GHz 7-Bit High-Linearity Phase Rotator Based on Wideband Injection-Locking Multi-Phase Generation for High-Speed Serial Links in 28-nm CMOS FDSOI

Another article in this issue, the introductory article by Tony Chan Carusone, discussed how the limited bandwidth of an electrical channel causes distortion (e.g., broadening) of the pulses traveling from transmitter to receiver. Without compensating for such distortion, the maximum data rate of a typical electrical link would be limited to only a few gigabits per second to avoid excessive intersymbol interference (ISI). The key to achieving dramatically higher data rates (up to 56 Gb/s in the latest proposed standards) is to employ channel equalization. This article describes the most common types of equalizers used in electrical links today.

Equalization for Electrical Links: Current Design Techniques and Future Directions

This paper presents a fully packaged 140-GHz dielectric waveguide (DWG) communication link using a foam-cladded fiber. A novel frequency shift keying (FSK) demodulator topology is proposed with a low-frequency feedback loop for optimal FSK demodulation under process, voltage, and temperature variation. The introduction of phase shifters and an on-chip local oscillator relaxes the design requirements and the IF-stage benefits from larger gain. The transmitter is based on a fundamental oscillator at 140 GHz with a transformer-coupled buffer to decrease capacitive loading. Both chips are implemented in a 28-nm bulk CMOS design with a nominal supply of 0.9 V and a combined power consumption of 230 mW. An analysis of the DWG data capacity limitations is presented and compared with measurement results. Data rates of 12 Gb/s/10 Gb/s/7 Gb/s over 1 m/2 m/4 m of touchable polytetrafluoroethylene (PTFE) fiber are achieved.

Analysis and Design of a Foam-Cladded PMF Link With Phase Tuning in 28-nm CMOS

The amount of data traffic is increasing year by year as the number of data-rich services like cloud services and streaming services are increasing. The number of switch modules between servers should decrease to lower latency, and several servers in each rack should be connected to one switch module with cables in a data centre. Using copper cables to connect racks is attractive in terms of cost minimization. Thin cables, for example 34 AWG copper cables, make maintenance easy. The cable length should be 5–7m to connect between racks, and 34 AWG 7m cable has 48dB loss, including board trace loss, package loss and so on. So far transceivers over 25Gb/s, equalizing 35–40dB channel loss have been proposed [1–4], with which low-loss cables like 26 AWG have been required. We target a 25Gb/s transceiver equalizing over 50dB channel loss, and adopt a sub-mV dynamic DC offset cancelation and a decision-feedback equalizer (DFE) with a bias-controlled tap slicer. Both improve on the minimum input sensitivity and enable data transmission through a channel with over 50dB loss.

3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS

As processing and network speeds are accelerated to support data-rich services, the bandwidth of backplane interconnects needs to be increased while maintaining the channel length and multi-rate links. However, channel losses and impedance discontinuities increase at high data-rates, making it difficult to compensate the channel. In this work, we target serial links from auto-negotiation in 100G-KR4 of 0.3Gb/s to 32GFC of 28.05Gb/s in 40dB backplane architecture [1-3]. To achieve this challenge, there are two key techniques. First, we introduce a 36-tap decision-feedback equalizer (DFE) to cancel reflections due to connectors because these reflections close the eye. To operate the 36-tap DFE, we need to fix a CDR lock-point and calculate 36-tap coefficients accurately. Thus, we develop a pattern-captured CDR with a 4b pattern filter to fix the lock-point, and a 3b pattern-matched adaptive equalizer (AEQ) to optimize 36 tap coefficients. These techniques enable our chip to compensate 40dB channel loss. Second, we target 100G-KR4/40G-KR4/10G-KR/25G-KR and 32GFC/16GFC/8GFC/4GFC. To operate across a wide range of data-rates, from 0.3 to 28.05Gb/s, with low jitter, we develop a PLL architecture with two LC-VCOs and one ring VCO with a data-rate-adjustment technique by controlling an LDO. Our test chip is fabricated in 28nm CMOS. Our signal conditioner is the demonstration to achieve the BER <1012 PRBS31 at 100G-KR4 in a 40dB chip-to-chip backplane with two connectors by using the 36-tap DFE to cancel the reflection and to operate across a wide range of data-rates from 0.3 to 28.05Gb/s.

3.2 multi-standard 185fs rms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS

A 25-Gbps/lane 40-dB compensation signal conditioner was developed. The target architecture was a long channel backplane with two connectors that have large reflections due to impedance discontinuities. Jitters originating from the power integrity (PI) and signal integrity (SI) are critical for a bit error rate (BER) less than 1E-12 because 1 unit interval (UI) is small at high speed. A technique for frequency dependent decap was designed to reduce the PI jitter. Also, a non-linear equalization for the reflections technique was designed to reduce the SI jitter. Our test chip can achieve 2.5 ps PI and 10.0 ps SI jitter, respectively. The sum of the PI and SI jitter can be reduced to less than 0.32 UI. Finally, our test chip can achieve a BER of less than 1E-12 for a 40-dB backplane with two connector traces.

Power, signal integrity for 25-Gbps, 40-dB compensation signal conditioner for backplane architecture

We developed a long channel backplane 28 Gbps transmission technology for next-generation high-speed I/O applications. To achieve long-channel backplane traces at 28 Gbps, main jitter sources such as ISI, crosstalk, power supply noise, and circuit origin including random jitter need to be drastically reduced. Among these, ISI is the largest jitter source. It is important to not only compensate for loss of channel but also reduce reflections due to impedance mismatch. Therefore, we proposed a low-jitter implementation technology for a package (PKG) and a print circuit board (PCB). This technique is a method to buffer the impedance mismatch by the impedance drop of a solder ball at high-speed transmission. By using the proposed technique, the ISI jitter can reduce 1 ps and EYE opening margin can be made larger than 0.04 UI.

Norio Nakajima

Papers

3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS

3.2 multi-standard 185fs rms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS

Power, signal integrity for 25-Gbps, 40-dB compensation signal conditioner for backplane architecture

Impedance matching method for jitter reduction of 28Gbps retimer