T
Takashi Kawamoto
Researcher at Hitachi
Publications - 27
Citations - 197
Takashi Kawamoto is an academic researcher from Hitachi. The author has contributed to research in topics: Jitter & Clock generator. The author has an hindex of 6, co-authored 25 publications receiving 187 citations.
Papers
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Proceedings ArticleDOI
Spread-spectrum clock generator for serial ATA using fractional PLL controlled by /spl Delta//spl Sigma/ modulator with level shifter
Masaru Kokubo,Takashi Kawamoto,Takashi Oshima,T. Noto,M. Suzuki,S. Suzuki,T. Hayasaka,Tomoaki Takahashi,J. Kasai +8 more
TL;DR: In this paper, the spread-spectrum clock generator uses the fractional PLL controlled by a /spl Delta/spl Sigma/ modulator and an adaptive level shifter is adopted for expanding the input range of the modulator.
Proceedings ArticleDOI
3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS
Takayasu Norimatsu,Takashi Kawamoto,Kenji Kogo,Naohiro Kohmu,Fumio Yuki,Norio Nakajima,Takashi Muto,Junya Nasu,Takemasa Komori,Hideki Koba,Tatsunori Usugi,Tomofumi Hokari,Tsuneo Kawamata,Yuichi Ito,Seiichi Umai,Masatoshi Tsuge,Takeo Yamashita,Masatoshi Hasegawa,Keiichi Higeta +18 more
TL;DR: A 25Gb/s transceiver equalizing over 50dB channel loss is targeted, and a sub-mV dynamic DC offset cancelation and a decision-feedback equalizer (DFE) with a bias-controlled tap slicer are adopted to improve on the minimum input sensitivity and enable data transmission through a channel with over 50 dB loss.
Proceedings ArticleDOI
3.2 multi-standard 185fs rms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS
Takashi Kawamoto,Takayasu Norimatsu,Kenji Kogo,Fumio Yuki,Norio Nakajima,Masatoshi Tsuge,Tatsunori Usugi,Tomofumi Hokari,Hideki Koba,Takemasa Komori,Junya Nasu,Tsuneo Kawamata,Yuichi Ito,Seiichi Umai,Jun Kumazawa,Hiroaki Kurahashi,Takashi Muto,Takeo Yamashita,Masatoshi Hasegawa,Keiichi Higeta +19 more
TL;DR: The signal conditioner is the demonstration to achieve the BER <;1012 PRBS31 at 100G-KR4 in a 40dB chip-to-chip backplane with two connectors by using the 36-tap DFE to cancel the reflection and to operate across a wide range of data-rates from 0.3 to 28.05Gb/s.
Journal ArticleDOI
Spread-Spectrum Clock Generator for Serial ATA with Multi-Bit ΣΔ Modulator-Controlled Fractional PLL
Masaru Kokubo,Takashi Kawamoto,Takashi Oshima,Takayuki Noto,Masato Suzuki,Shigeyuki Suzuki,Takashi Hayasaka,Tomoaki Takahashi,Jun Kasai +8 more
TL;DR: A spread-spectrum Phase-Locked Loop (PLL) for serial ATA applications was developed and a combination of small jitter and large electromagnetic interference (EMI) peak power reduction was achieved and showed that the spread-Spectrum generator more than satisfiesserial ATA specifications.
Patent
Power circuit used for an amplifier
Yoichi Okubo,Manabu Nakamura,Junya Dosaka,Yasuhiro Takeda,Taizo Ito,Naoki Hongo,Taizo Yamawaki,Takashi Kawamoto,Akira Maeki +8 more
TL;DR: In this paper, a power circuit used for an amplifier, which includes an amplifier provided with a linear amplifier serving as a voltage source, a DC/DC converter serving as current source, and a hysteresis comparator controlling the DC and DC converter, is described.