T
Takemasa Komori
Researcher at Hitachi
Publications - 4
Citations - 57
Takemasa Komori is an academic researcher from Hitachi. The author has contributed to research in topics: Phase-locked loop & Digital clock manager. The author has an hindex of 3, co-authored 4 publications receiving 50 citations.
Papers
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Proceedings ArticleDOI
3.3 A 25Gb/s multistandard serial link transceiver for 50dB-loss copper cable in 28nm CMOS
Takayasu Norimatsu,Takashi Kawamoto,Kenji Kogo,Naohiro Kohmu,Fumio Yuki,Norio Nakajima,Takashi Muto,Junya Nasu,Takemasa Komori,Hideki Koba,Tatsunori Usugi,Tomofumi Hokari,Tsuneo Kawamata,Yuichi Ito,Seiichi Umai,Masatoshi Tsuge,Takeo Yamashita,Masatoshi Hasegawa,Keiichi Higeta +18 more
TL;DR: A 25Gb/s transceiver equalizing over 50dB channel loss is targeted, and a sub-mV dynamic DC offset cancelation and a decision-feedback equalizer (DFE) with a bias-controlled tap slicer are adopted to improve on the minimum input sensitivity and enable data transmission through a channel with over 50 dB loss.
Proceedings ArticleDOI
3.2 multi-standard 185fs rms 0.3-to-28Gb/s 40dB backplane signal conditioner with adaptive pattern-match 36-Tap DFE and data-rate-adjustment PLL in 28nm CMOS
Takashi Kawamoto,Takayasu Norimatsu,Kenji Kogo,Fumio Yuki,Norio Nakajima,Masatoshi Tsuge,Tatsunori Usugi,Tomofumi Hokari,Hideki Koba,Takemasa Komori,Junya Nasu,Tsuneo Kawamata,Yuichi Ito,Seiichi Umai,Jun Kumazawa,Hiroaki Kurahashi,Takashi Muto,Takeo Yamashita,Masatoshi Hasegawa,Keiichi Higeta +19 more
TL;DR: The signal conditioner is the demonstration to achieve the BER <;1012 PRBS31 at 100G-KR4 in a 40dB chip-to-chip backplane with two connectors by using the 36-tap DFE to cancel the reflection and to operate across a wide range of data-rates from 0.3 to 28.05Gb/s.
Journal ArticleDOI
A 100-Gbps 4-Lane Transceiver for 47-dB Loss Copper Cable in 28-nm CMOS
TL;DR: A 103-Gbps 4-lane transceiver for copper cable applications was fabricated in 28-nm CMOS technology and a DFE with a bias controlled tap slicer is proposed, which improves the SNR at the slicer’s input and reduces the dead zone of CDR phase detector.
Patent
Skew adjustment circuit, semiconductor device, and skew calibration method
TL;DR: In this article, a skew adjustment circuit is proposed to adjust the phases of second clock signals, based on the second clock signal generated based on a reference clock signal and an output signal from the flip flop circuits.