Nourhan Elhamawy

TL;DR: In this article, the authors consolidate available knowledge about what system-level test is precisely and why it is used despite its considerable costs and complexities, and outline approaches to quality assessment, test generation and root-cause diagnosis in the context of SLT.

TL;DR: System-level test, or SLT, is an increasingly important process step in today’s integrated circuit testing flows and new and promising directions for methodical developments leveraging on recent findings from software engineering are outlined.

TL;DR: In this paper, the authors present the potential of RISC-V in security research, the way in which RISCv can be hardened against power analysis attacks, how to implement, using RISCV, software and hardware/software solutions for dual core lock step, and how to perform system-level testing in the RISC V ecosystem.

TL;DR: A scalable, area-optimized elliptic curve ElGamal cryptosystem module that integrates both the encryption and decryption operations into a single block and supports the NIST-recommended curves over prime fields.

TL;DR: In this article , the use of RISC-V processors for safety-related applications is discussed and the essential techniques necessary to obtain safety both in the functional and in the timing domain.