Oguz Ergin

TL;DR: This work develops a low-cost mechanism, called ChargeCache, that enables faster access to recently- accessed rows in DRAM, with no modifications to DRAM chips, based on the key observation that a recently-accessed row has more charge and thus the following access to the same row can be performed faster.

TL;DR: The first publicly-available DRAM testing infrastructure that can flexibly and efficiently test DRAM chips in a manner accessible to both software and hardware developers is developed, SoftMC (Soft Memory Controller), an FPGA-based testing platform that can control and test memory modules designed for the commonly-used DDR interface.

TL;DR: GRIM-Filter as discussed by the authors uses 3D-stacked memory to improve the performance of a read mapper by introducing a new representation of coarse-grained segments of the reference genome, and using massively-parallel in-memory operations to identify read presence within each coarsegrained segment.

TL;DR: Variability must be considered at both the circuit and micro-architectural design levels to keep pace with performance scaling and to keep power consumption within reasonable limits as mentioned in this paper, and an overview of the main sources of variability can be found in this paper.

TL;DR: In this article, the authors propose an enhancement to the above technique by leveraging the notion of short-lived operands (values targeting the registers that are renamed by the time the instruction producing the value reaches the writeback stage).