O
Olaf Bonorden
Researcher at University of Paderborn
Publications - 10
Citations - 284
Olaf Bonorden is an academic researcher from University of Paderborn. The author has contributed to research in topics: Parallel algorithm & Load balancing (computing). The author has an hindex of 8, co-authored 10 publications receiving 284 citations.
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The Paderborn University BSP (PUB) library
TL;DR: The Paderborn University BSP (PUB) library is a C communication library based on the BSP model that supports buffered as well as unbuffered non-blocking communication between any pair of processors and a mechanism for synchronizing the processors in a barrier style.
Proceedings ArticleDOI
The Paderborn university BSP (PUB) library-design, implementation and performance
TL;DR: The Paderborn University BSP (PUB) library is a parallel C library based on the BSP model that provides routines for collective communication on arbitrary subsets of processors, partition operations, and a zero-cost synchronization mechanism.
Journal Article
A web computing environment for parallel algorithms in java
TL;DR: PUBWCL as mentioned in this paper is a web computing library in Java that allows to execute strongly coupled, massively parallel algorithms in the bulk-synchronous (BSP) style on PCs distributed over the internet whose owners are willing to donate their unused computation power.
Journal Article
Load balancing strategies in a web computing environment
TL;DR: This work evaluated the load balancing algorithms using the web computing library for BSP programs in Java (PUBWCL) with the best performing load balancing strategy saving 39% of the execution time averaged and even up to 50% in particular cases.
Proceedings ArticleDOI
A holistic methodology for network processor design
Olaf Bonorden,N. Bruls,Uwe Kastens,Dinh Khoi Le,F.M. auf der Heide,J.-C. Niemann,Mario Porrmann,Ulrich Rückert,Adrian Slowik,Michael Thies +9 more
TL;DR: A design methodology for network processors which encompasses the research areas from the application software down to the gate level of the chip is presented.